# 3DIC Device Development Engineer at Intel

Intel is hiring a 3DIC Device Development Engineer. It pays $137k-$269k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/973eb9e9-d80f-49cf-b674-731bdea353e1?utm_medium=ai-agent).

AI Level 1, AI centrality 30 out of 100. US, Oregon, Hillsboro.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 30 out of 100)
- Location: US, Oregon, Hillsboro
- Salary: $137k-$269k
- Posted: November 10, 2026
- Apply: https://jobsbylevel.com/go/973eb9e9-d80f-49cf-b674-731bdea353e1?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=3dic-device-development-engineer-at-intel-611773

## Description

Job Details: Job Description: About the Team Manufacturing Development and Customer Engineering (MDCE) serves as the critical bridge between Technology Development (TD) and High Volume Manufacturing (HVM) within Intel Foundry. The organization is responsible for transitioning leading-edge technologies from development and qualification into high-yield production while enabling successful deployment for foundry customers. The MDCE Device Team is expanding its 3DIC device engineering capabilities and is seeking an experienced engineer to drive device understanding and optimization for advanced 3D integration technologies. Position Overview As a 3DIC Device Development Engineer, you will be responsible for understanding, characterizing, and modeling the impact of advanced 3D integration technologies on transistor and passive device performance. Technologies such as through-silicon vias (TSVs), hybrid bonding, active base die architectures, wafer thinning, and backside power delivery introduce new mechanical, thermal, and electrical interactions that influence device behavior, variability, and reliability. In this role, you will transform complex silicon data into actionable insights, design rules, device collateral, and customer-ready guidance that support next-generation products including AI accelerators, high-performance computing solutions, and high-bandwidth memory (HBM) platforms. Key Responsibilities Responsibilities include, but are not limited to: Characterize and model the impact of advanced 3D integration technologies, including TSVs, hybrid bonding, wafer thinning, and backside processing, on device performance metrics such as mobility, threshold voltage (Vt), leakage, matching, and variability. Evaluate stress, thermal, and electrical coupling effects, including keep-out zone (KOZ) behavior and device interactions within complex 3D stacks. Define and develop device and passive test structures to study 3DIC effects, including TSV proximity, KOZ, guard ring, resistor, and capacitor structures. Drive electrical test (e-test) strategy, data collection, and silicon analysis to accelerate technology learning and optimization. Provide device characterization inputs that enable design rule development, compact models, PDKs, and 3D design kit releases in collaboration with Design Enablement teams. Partner closely with Process Integration, Packaging, Assembly, Reliability, Yield, and Program Management organizations to identify, troubleshoot, and resolve device-related issues. Evaluate customer requirements for analog, mixed-signal, RF, and high-speed I/O devices within 3D architectures, assessing technical feasibility, risk, and implementation timelines. Support technology qualification and manufacturing readiness activities, including device targeting, monitoring strategies, yield improvement efforts, and excursion management. Communicate complex technical findings and recommendations to engineering, business, and customer stakeholders. What We Are Looking For The successful candidate will demonstrate: Deep understanding of CMOS device physics and the impact of process, stress, and thermal effects on device performance. Strong analytical and problem-solving skills, including data science, statistical analysis, and scripting capabilities. Excellent written and verbal communication skills with the ability to explain complex technical concepts to diverse audiences. Proven ability to influence and collaborate across device, process, packaging, manufacturing, and design organizations. Strong ownership mindset, technical curiosity, and a passion for developing innovative solutions in advanced semiconductor technologies. Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/3dic-device-development-engineer-at-intel-611773

Source: https://jobsbylevel.com/jobs/3dic-device-development-engineer-at-intel-611773

## Cite this page

Level. https://jobsbylevel.com/jobs/3dic-device-development-engineer-at-intel-611773.

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