# Advanced Packaging Design Engineer (Hybrid) at Cisco

Cisco is hiring an Advanced Packaging Design Engineer (Hybrid) in San Jose, United States. It pays $155k-$223k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/d13a8a0c-173d-48bf-9b78-803ee02c27cb?utm_medium=ai-agent).

AI Level 1, AI centrality 35 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 35 out of 100)
- Location: San Jose, California, US
- Salary: $155k-$223k
- Posted: November 10, 2026
- Apply: https://jobsbylevel.com/go/d13a8a0c-173d-48bf-9b78-803ee02c27cb?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=advanced-packaging-design-engineer-hybrid-at-cisco-2140a5

## Description

The application window is expected to close on: 01/28/2027 This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! Your Impact In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions. You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment. Responsibilities Contribute to package design activities including planning, floor planning, pinout optimization, stack‑up definition, and high‑speed routing support. Collaborate with SI/PI, silicon floor planning, layout, and manufacturing teams to ensure high‑quality package solutions. Support package implementation activities and work closely with layout editors to ensure alignment between design intent and physical implementation. Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations. Assist in developing and improving package design methodologies, flows, and best practices. Contribute to debugging, issue resolution, and package bring‑up activities as needed. Work with package leads and senior engineers on complex package programs and progressively take ownership of larger design scopes. Minimum Qualifications Bachelor’s with 5+ years of experience or Master’s degree with 3+ years of experience in Electrical Engineering or a related field. Experience in hardware, package, PCB, or high‑speed design engineering. Experience of high‑speed signaling, power delivery, and system-level hardware concepts. Prior experience with industry-standard EDA tools for package or PCB design. Preferred Qualifications Experience in ASIC package design, PCB design, or related high‑speed hardware development. Experience with SI/PI concepts and collaboration with cross‑functional engineering teams. Experience with advanced packaging technologies, interposers, or multi‑die systems is an advantage. Experience with scripting languages such as (Python, Perl, TCL, or shell). Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/advanced-packaging-design-engineer-hybrid-at-cisco-2140a5

Source: https://jobsbylevel.com/jobs/advanced-packaging-design-engineer-hybrid-at-cisco-2140a5

## Cite this page

Level. https://jobsbylevel.com/jobs/advanced-packaging-design-engineer-hybrid-at-cisco-2140a5.

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