# Advanced Packaging Design Engineering Team Leader (Hybrid) at Cisco

Cisco is hiring an Advanced Packaging Design Engineering Team Leader (Hybrid) in San Jose, United States. It pays $214k-$310k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/bccee394-95fe-4100-8197-4083baa9e5fc?utm_medium=ai-agent).

AI Level 1, AI centrality 35 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 35 out of 100)
- Location: San Jose, California, US
- Salary: $214k-$310k
- Posted: October 26, 2026
- Apply: https://jobsbylevel.com/go/bccee394-95fe-4100-8197-4083baa9e5fc?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=advanced-packaging-design-engineering-team-leader-hybrid-at-cisco-c4c115

## Description

The application window is expected to close on: 01/28/2027 This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! Your Impact This role offers a unique opportunity to make a significant impact on the future of networking innovation within the Cisco Silicon One initiative. As a technical and team leader, you will drive complex package design programs—from planning and optimization to execution—ensuring the delivery of high-speed, robust, and scalable solutions for global networks. You will lead and grow the San Jose package design team, mentoring engineers and developing future package leads while collaborating closely with layout, SI/PI, silicon architecture, and manufacturing partners. Your leadership will ensure the delivery of high-quality package designs aligned with system-level requirements. Beyond technical leadership, you will help shape methodologies, improve development flows, and strengthen cross-functional collaboration across Cisco’s global silicon organization, while fostering a culture of collaboration, accountability, and continuous improvement. Lead complex package design programs, planning and driving schedules from concept through implementation and tapeout. Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance, manufacturability, and reliability. Collaborate with silicon floor planning, signal integrity (SI), and power integrity (PI) teams to ensure design quality and system-level alignment. Work closely with layout editors and implementation teams to deliver high-quality package layouts aligned with interface and manufacturing requirements. Serve as the technical and organizational leader of the San Jose package design team, providing direction, mentorship, and technical guidance to engineers. Develop and grow package design capability within the team, mentoring engineers and enabling them to take ownership of increasingly complex package programs. Coordinate resources across designers, layout editors, and contractors to support efficient project execution. Enhance package design methodologies and partner with vendors to improve product quality and efficiency. Drive innovation in package solutions for Cisco’s next-generation ASIC platforms. Minimum Qualifications Bachelor’s degree in electrical engineering or a related field with 12+ years of work experience or Master’s degree in Electrical Engineering or a related field with 8+ years of work experience Experience in high-speed package design, including signal integrity considerations and power distribution networks (PDN). Experience with industry-standard EDA tools for package layout and design. Experience with technical leadership in complex hardware or silicon development programs. Preferred Qualifications Extensive experience in ASIC package design, including pinout optimization and high-speed routing. Knowledge

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/advanced-packaging-design-engineering-team-leader-hybrid-at-cisco-c4c115

Source: https://jobsbylevel.com/jobs/advanced-packaging-design-engineering-team-leader-hybrid-at-cisco-c4c115

## Cite this page

Level. https://jobsbylevel.com/jobs/advanced-packaging-design-engineering-team-leader-hybrid-at-cisco-c4c115.

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