# Advanced Packaging Layout Engineering Team Leader (Substrate & Interposer) (Hybrid) at Cisco

Cisco is hiring an Advanced Packaging Layout Engineering Team Leader (Substrate & Interposer) (Hybrid) in San Jose, United States. It pays $214k-$310k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/cee68f54-f526-4d68-a9cb-d5c7da5db065?utm_medium=ai-agent).

AI Level 1, AI centrality 37 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 37 out of 100)
- Location: San Jose, California, US
- Salary: $214k-$310k
- Posted: October 26, 2026
- Apply: https://jobsbylevel.com/go/cee68f54-f526-4d68-a9cb-d5c7da5db065?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=advanced-packaging-layout-engineering-team-leader-substrate-interposer-hybrid-at-cisco-035d88

## Description

The application window is expected to close on: 01/28/2027 This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry! Your Impact As a Packaging Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide hands-on technical guidance, mentorship, resource coordination, and people leadership for package layout activities across advanced ASIC packaging and CoWoS projects. Working closely with package leads, SI/PI teams, and the global layout organization, you will help strengthen layout engineering capability, improve methodologies and flows, and support high‑quality package implementations. This role combines technical leadership, team development, and cross‑functional collaboration in a fast‑paced and highly collaborative engineering environment. Lead and support the San Jose package layout team, providing hands-on technical guidance, mentorship, and day‑to‑day support to layout engineers. Drive hands-on package layout activities for complex ASIC advanced packaging, including CoWoS projects, ensuring high‑quality implementation aligned with package design, SI/PI, and manufacturing requirements. Collaborate closely with package leads, SI/PI teams, silicon floor planning, and manufacturing partners to resolve technical and process challenges. Coordinate layout resource allocation, priorities, and staffing across multiple concurrent projects. Support optimization of package pinouts, stack‑ups, power distribution, escape routing, CoWoS interposers, and high‑speed interface implementation. Partner with the global Package Layout Manager and other regional leaders to align methodologies, tools, best practices, and engineering standards across sites. Contribute to hiring, onboarding, mentoring, and development of layout engineering talent in San Jose. Work with vendors and contractors as needed to support project execution and delivery goals. Drive continuous improvement in layout methodologies, quality, and engineering efficiency. Minimum Qualifications Bachelor’s degree in Electrical Engineering or a related field with 12+ years of work experience or a Master’s degree in Electrical Engineering or a related field with 8+ years of work experience or a PhD in Electrical Engineering or a related field with 5+ years of work experience. 5+ years of experience in package layout or advanced PCB/package implementation. Prior experience working with high‑speed routing, power distribution networks (PDN), and package layout design principles. Experience with industry‑standard EDA tools for package layout and design. Hands-on experience with Cadence APD+ or equivalent package layout tools Preferred Qualifications Experience leading or mentoring layout engineers or small technical teams. Experience with ASIC package substrate layout implementation and CoWoS , including

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/advanced-packaging-layout-engineering-team-leader-substrate-interposer-hybrid-at-cisco-035d88

Source: https://jobsbylevel.com/jobs/advanced-packaging-layout-engineering-team-leader-substrate-interposer-hybrid-at-cisco-035d88

## Cite this page

Level. https://jobsbylevel.com/jobs/advanced-packaging-layout-engineering-team-leader-substrate-interposer-hybrid-at-cisco-035d88.

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