# ASIC Design Engineer I (Intern) - United States at Cisco

Cisco is hiring an ASIC Design Engineer I (Intern) - United States in San Jose, United States. Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/24a3a166-1410-4eaa-a3d9-cbcfdda33f60?utm_medium=ai-agent).

AI Level 1, AI centrality 34 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 34 out of 100)
- Location: San Jose, California, US
- Posted: October 14, 2026
- Apply: https://jobsbylevel.com/go/24a3a166-1410-4eaa-a3d9-cbcfdda33f60?utm_medium=ai-agent

## Description

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Engineer, you will play a pivotal role in designing and integrating next-generation silicon for Cisco’s core networking products. You’ll contribute to all phases of the ASIC design lifecycle, collaborating with cross-functional teams to ensure robust, high-performance solutions. You will: Participate in the creation of design specifications and in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and support timing methodology and analysis. Develop, analyze, and ensure functional coverage. Collaborate with the verification team to address design bugs and close code coverage. Collaborate with the physical design team to resolve timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post-silicon validation tests in the lab. Minimum Qualifications Currently enrolled in an undergraduate degree program (Associate's or Bachelor's) Qualifying education should be in ASIC Design, Engineering or a related field. Expected to continue enrollment in degree program following completion of the internship. Foundational knowledge and academic project experience in Verilog/SystemVerilog Demonstrated ability to perform interactive and wave-form based debugging on digital systems Preferred Qualifications Proficiency in scripting languages such as Python, Perl, TCL, or shell for task automation. Coursework or project experience related to networking protocols and architectures. Excellent written and verbal communication skills with the ability to collaborate effectively in a team environment. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-design-engineer-i-intern-united-states-at-cisco-e4021b

Source: https://jobsbylevel.com/jobs/asic-design-engineer-i-intern-united-states-at-cisco-e4021b

## Cite this page

Level. https://jobsbylevel.com/jobs/asic-design-engineer-i-intern-united-states-at-cisco-e4021b.

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