# ASIC Design Engineer Technical Lead at Cisco

Cisco is hiring an ASIC Design Engineer Technical Lead in San Jose, United States. It pays $187k-$268k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/a2aeda51-39eb-4118-85d0-c5a74fbecdef?utm_medium=ai-agent).

AI Level 1, AI centrality 20 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 20 out of 100)
- Location: San Jose, California, US
- Salary: $187k-$268k
- Posted: July 28, 2026
- Apply: https://jobsbylevel.com/go/a2aeda51-39eb-4118-85d0-c5a74fbecdef?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-design-engineer-technical-lead-at-cisco-15fa6a

## Prepare for this job

The job page lists 5 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/asic-design-engineer-technical-lead-at-cisco-15fa6a

## Description

The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support our design methodology. Mentor junior engineers on performing project tasks and problem solving. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post silicon validation tests in the lab. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design experience. Verilog/System Verilog programming experience. Interactive and waveform debug experience. Experience delivering ASIC designs from specification to tape-out. Experience in architecture and micro architecture development. Preferred Qualifications Experience resolving setup and hold timing violations with RTL modification. Scripting experience (Python, Perl, TCL, shell programming). Demonstrated ability in troubleshooting and debugging. Good written and verbal communication skills. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-design-engineer-technical-lead-at-cisco-15fa6a

Source: https://jobsbylevel.com/jobs/asic-design-engineer-technical-lead-at-cisco-15fa6a

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