# ASIC DFT Engineer - Acacia (Hybrid) at Cisco

Cisco is hiring an ASIC DFT Engineer - Acacia (Hybrid) in San Jose, United States. It pays $155k-$223k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/69745655-325b-4b94-8a6e-27364b794a9b?utm_medium=ai-agent).

AI Level 1, AI centrality 32 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 32 out of 100)
- Location: San Jose, California, US
- Salary: $155k-$223k
- Posted: October 27, 2026
- Apply: https://jobsbylevel.com/go/69745655-325b-4b94-8a6e-27364b794a9b?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-dft-engineer-acacia-hybrid-at-cisco-195e6c

## Description

This is a hybrid role than can be performed three days per week from our San Jose, CA office. Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic Run DFT rule checks and debug scan, clock, reset, and test-mode issues Generate and validate ATPG patterns for stuck-at, transition, and other required fault models Analyze test coverage, pattern count, compression results, and ATPG reports Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues Work with RTL and verification teams to ensure DFT requirements are correctly implemented Support block-level and full-chip DFT integration activities Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting Support silicon debug, diagnosis analysis, and yield-learning activities as needed Document DFT implementation results, known issues, waivers, and signoff status Minimum Qualifications: Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience. Experience with ASIC DFT implementation or validation Experience with industry DFT tools such as Siemens Tessent , Synopsys DFT Compiler/TestMAX , or equivalent Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls Experience with stuck-at and transition fault models Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures Scripting experience using Tcl, Python, Perl, or shell Preferred Qualifications Experience with hierarchical DFT methodology and block-level signoff Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows Experience with MBIST insertion, memory test validation, or BISR flows Familiarity with gate-level simulation, SDF timing, and pattern validation Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs Ability to improve automation, regression checks, and DFT reporting dashboards Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation Scripting experience using Tcl, Python, Perl, or shell Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-dft-engineer-acacia-hybrid-at-cisco-195e6c

Source: https://jobsbylevel.com/jobs/asic-dft-engineer-acacia-hybrid-at-cisco-195e6c

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