# ASIC DFT Engineer I (Full Time) - United States at Cisco

Cisco is hiring an ASIC DFT Engineer I (Full Time) - United States in San Jose, United States. Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/4fb9c867-2250-4ae0-b1b2-f9161d8a1cfe?utm_medium=ai-agent).

AI Level 1, AI centrality 32 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 32 out of 100)
- Location: San Jose, California, US
- Posted: November 6, 2026
- Apply: https://jobsbylevel.com/go/4fb9c867-2250-4ae0-b1b2-f9161d8a1cfe?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-dft-engineer-i-full-time-united-states-at-cisco-f0a8c0

## Description

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will: Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs. Create and enhance automation scripts to improve implementation robustness and efficiency. Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog. Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis. Minimum Qualifications A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months ). Qualifying education should be in ASIC DFT or a related field. Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan). Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl. Experience working with gate-level simulations and debugging using simulators like VCS. Preferred Qualifications Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation. Understanding of basic VLSI circuit physical behaviors in silicon (such as electromigration and temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability). Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis. Strong verbal and written communication skills to collaborate effectively with frontend RTL, backend physical design, and verification teams. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-dft-engineer-i-full-time-united-states-at-cisco-f0a8c0

Source: https://jobsbylevel.com/jobs/asic-dft-engineer-i-full-time-united-states-at-cisco-f0a8c0

## Cite this page

Level. https://jobsbylevel.com/jobs/asic-dft-engineer-i-full-time-united-states-at-cisco-f0a8c0.

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