# ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore) at Cisco

Cisco is hiring an ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore) (India). Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/3dc1b662-bee3-45ad-b5a0-6db4f6c04979?utm_medium=ai-agent).

AI Level 1, AI centrality 10 out of 100. Pune, India.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 10 out of 100)
- Location: Pune, India
- Posted: May 21, 2026
- Apply: https://jobsbylevel.com/go/3dc1b662-bee3-45ad-b5a0-6db4f6c04979?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-engineering-digital-designer-leader-digital-design-fsm-cpu-sub-systems-complex-socs-8-12-years-pune-bangalore-at-cisco-b6496f

## Prepare for this job

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## Description

Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. What You'll Do The Digital Design Lead for the Client Optics Group (COG) provides essential technical leadership in the development of digital logic for silicon photonics, ensuring high-performance outcomes for 100G, 200G, and 400G optical interconnects. This role involves managing the full ASIC lifecycle, from architectural conception and RTL-based design of CPU subsystems and data path interfaces to tapeout and post-silicon production support, while overseeing the integration of digital logic with analog and mixed-signal blocks to ensure the reliability of Co-Packaged Optics and silicon photonics modules. Candidates must possess comprehensive expertise in high-speed optical interconnects and mastery of the complete ASIC/SoC design flow, including DFT, physical design, and verification. Furthermore, the position requires the ability to drive technical strategy through effective collaboration with cross-functional teams in firmware, packaging, and process engineering to optimize power, performance, and manufacturability within the United States of America office context. Your Impact As a senior level individual contributor, you will work with a diverse team of engineers spanning digital design, analog/mixed-signal design, verification, DFT, physical design, firmware, FPGA, CAD, packaging, and post-silicon validation. At the concept stage, you will help define the digital architecture, interface requirements, implementation strategy, and design methodology. During execution, you will own block level and top-level design and block level verification, and support full-chip integration of high-speed IPs such as ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will work closely with verification teams to ensure complete functional closure, with physical design teams to support implementation readiness, and with post-silicon teams to help drive successful product bring-up and release to production. Specific responsibilities include Contribute individually during all design activities from Pre-Silicon RTL to GDS2 signoff and post-silicon activities such as FPGA prototyping, Lab Validation and ATE bring-up. Design complex digital blocks and CPU subsystems. Work seamlessly across cross function teams and resolve design and technical issues. Must be able to understand concepts such as accuracy, resolution, loop time constants and make appropriate trade-offs. Propagate top level specifications to block level specifications for high speed datapath and low speed control planes, including timing, power budgets and hardware vs firmware partitioning Review verification coverage and sign off on coverage metrics. Independently simulate, verify and debug verification issues. Support integration and verification of Serdes and DSP IP. Support all backend activities such as synthesis, timing closure, DFT and low power design, scripts for design

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-engineering-digital-designer-leader-digital-design-fsm-cpu-sub-systems-complex-socs-8-12-years-pune-bangalore-at-cisco-b6496f

Source: https://jobsbylevel.com/jobs/asic-engineering-digital-designer-leader-digital-design-fsm-cpu-sub-systems-complex-socs-8-12-years-pune-bangalore-at-cisco-b6496f

## Cite this page

Level. https://jobsbylevel.com/jobs/asic-engineering-digital-designer-leader-digital-design-fsm-cpu-sub-systems-complex-socs-8-12-years-pune-bangalore-at-cisco-b6496f.

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