# ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid) at Cisco

Cisco is hiring an ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid) in San Jose, United States. It pays $155k-$223k a year and Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/6b588dfe-afb3-4c34-a28d-299ad355d9a1).

AI Level 1, AI centrality 28 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 28 out of 100)
- Location: San Jose, California, US
- Salary: $155k-$223k
- Posted: October 8, 2026
- Apply: https://jobsbylevel.com/go/6b588dfe-afb3-4c34-a28d-299ad355d9a1

## Description

The application window is expected to close on: 12/28/2026 This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! Your Impact We are seeking a qualified Signal and Power Integrity Engineer to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms. Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products. Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB. Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules. Minimum Qualifications Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience. High-Speed Design & Theory: Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction. SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS. Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation. Circuit Analysis: Experience with SPICE for circuit-level analysis, signal modeling, and performance validation. Preferred Qualifications Experience with articulating ideas and technical concepts to diverse audiences, both verbally and in writing. Experience with high-bandwidth memory (HBM) or high-speed memory interface SI. Experience with die-to-die interfaces (UCIe or proprietary). Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging. Experience with Vector Network Analysis. Experience with IBIS. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-packaging-signal-power-integrity-hardware-engineer-hybrid-at-cisco-416de6

Source: https://jobsbylevel.com/jobs/asic-packaging-signal-power-integrity-hardware-engineer-hybrid-at-cisco-416de6

## Cite this page

Level. https://jobsbylevel.com/jobs/asic-packaging-signal-power-integrity-hardware-engineer-hybrid-at-cisco-416de6.

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