# ASIC Physical Design Engineer at Cisco

Cisco is hiring an ASIC Physical Design Engineer in San Jose, United States. It pays $168k-$245k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/836a3157-7c83-4d8f-9d9f-8dc91b5b69eb?utm_medium=ai-agent).

AI Level 1, AI centrality 35 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 35 out of 100)
- Location: San Jose, California, US
- Salary: $168k-$245k
- Posted: November 12, 2026
- Apply: https://jobsbylevel.com/go/836a3157-7c83-4d8f-9d9f-8dc91b5b69eb?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-physical-design-engineer-at-cisco-ed5e41

## Description

The application window is expected to close on: 12/10/2026 Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will: Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm). Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies. Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools. Implement and manage timing ECO strategies using tools like Prime Closure/PrimeTime. Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements. Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency. Evaluate and implement new timing methodologies; provide creative debugging solutions. Contribute to best practices and drive methodology alignment across projects. Minimum Qualifications Bachelors degree in Electrical Engineering+ 5 years of related experience, or Masters degree in Electrical Engineering+ 2 years of related experience, or PhD in Electrical Engineering 0+ years of related experience. Hands-on experience in ASIC physical design and implementation. Experience working with hierarchical floorplanning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology. Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm). Preferred Qualifications Experience with Scripting using languages such as TCL, Python and efficient use of AI tools. Place & Route experience using tools such as Cadence Innovus or Synopsys FC. Synthesis experience including Cadence Genus/Synopsys FC. Formal Verification experience using tools such Synopsys Formality or Cadence LEC Experience with Static Timing Analysis including tools such as PrimeTime-DMSA. Experience with Power Integrity including tools such as Apache Redhawk/Voltus Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $167,700.00 to $245,200.00 and

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-physical-design-engineer-at-cisco-ed5e41

Source: https://jobsbylevel.com/jobs/asic-physical-design-engineer-at-cisco-ed5e41

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