# ASIC Power Design Engineer II (Full Time) - United States at Cisco

Cisco is hiring an ASIC Power Design Engineer II (Full Time) - United States in San Jose, United States. Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/42894ac5-b6a4-4490-bbe7-f396f5eb0303?utm_medium=ai-agent).

AI Level 1, AI centrality 31 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 31 out of 100)
- Location: San Jose, California, US
- Posted: November 3, 2026
- Apply: https://jobsbylevel.com/go/42894ac5-b6a4-4490-bbe7-f396f5eb0303?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-power-design-engineer-ii-full-time-united-states-at-cisco-c2a1eb

## Description

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications accepted until further notice. Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent). Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower (PTPX) across various operating modes, PVT corners, and functional activity scenarios (VCD/FSDB/SAIF). Collaborate closely with RTL design, architecture teams to identify power bottlenecks and guide RTL/micro-architectural power optimizations. Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA). Develop and maintain automated design and analysis workflows using Python, TCL, and Perl. Participate in post-silicon power and performance validation and correlation against pre-silicon PrimePower models. Minimum Qualifications Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience. (Relevant fields include ASIC Design or Power Design.) Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs). Proficiency with hardware description languages (SystemVerilog / Verilog). Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing. Familiarity with Linux/Unix development environment Preferred Qualifications Direct experience running activity-driven power analysis using FSDB/VCD/SAIF waveforms generated from gate-level and RTL simulations Experience with industry-standard EDA tools such as Synthesis & P&R: Synopsys Design Compiler, Fusion Compiler, IC Validator, or Cadence Innovus and Timing & Signoff: Synopsys Prime Time / Prime Time-SI, Prime Power, StarRC, Siemens Calibre. Experience with power integrity / IR-drop / EM analysis tools (e.g., Ansys RedHawk, Voltus). Understanding of sophisticated FinFET/GAA process node design rules and low-power library architectures. Excellent problem-solving, partnership, and communication skills within multi-functional teams Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-power-design-engineer-ii-full-time-united-states-at-cisco-c2a1eb

Source: https://jobsbylevel.com/jobs/asic-power-design-engineer-ii-full-time-united-states-at-cisco-c2a1eb

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Level. https://jobsbylevel.com/jobs/asic-power-design-engineer-ii-full-time-united-states-at-cisco-c2a1eb.

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