# ASIC Tech Lead (Analog) at LumAI

LumAI is hiring an ASIC Tech Lead (Analog). Level rates it Little AI ●○○○; you can [apply on LumAI](https://jobsbylevel.com/go/8c64b847-14c8-4c13-aba5-9ba363df3051?utm_medium=ai-agent).

AI Level 1, AI centrality 18 out of 100. EU - Multiple Locations.

## Details

- Company: [LumAI](https://jobsbylevel.com/companies/lumai)
- AI level: AI Level 1 (score 18 out of 100)
- Location: EU - Multiple Locations
- Posted: June 4, 2026
- Apply: https://jobsbylevel.com/go/8c64b847-14c8-4c13-aba5-9ba363df3051?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=asic-tech-lead-analog-at-lumai-a611c7

## Description

The Opportunity Lumai is scaling its custom silicon effort as it moves from first systems to volume production. The analog and mixed-signal blocks at the front of the accelerator - the receiver front-end, the data converters, the clocking and bias circuits - are what decide whether that silicon meets its power, performance and area targets. This role owns the technical direction of that work and the team that does it. The Role You will own the analog and mixed-signal IC development from architecture through tapeout to production. You will architect subsystems and take personal ownership of critical blocks, set and enforce the circuit methodologies, simulation corner strategies and layout guidelines the team works to, and own the analog side of tapeout sign-off. You will lead silicon bring-up and characterisation, and hold the technical relationships with the foundry, PDK and EDA partners. You will manage and mentor the analog team, and you report to the Head of Engineering. What is genuinely hard about this is that the analog content is not laid on top of a finished architecture. It develops alongside the photonics, digital and firmware work, so the electrical interfaces, calibration and real-time control loops are being fixed at the same time as the blocks that depend on them. The design has to be right the first time you can measure it, on a process node where device behaviour has to be understood rather than assumed. By month six, you will have the analog subsystems through their own design reviews with the methodologies and sign-off criteria agreed and written down, a bench plan ready for first silicon, and a team growing under you with a clear technical bar. What You'll Do Architect and own the analog and mixed-signal subsystems: TIA front-ends, VGAs, high-speed ADCs and DACs, PLLs, LDOs, bandgap references, and on-chip bias and calibration circuits. Lead circuit design from concept through schematic capture, pre- and post-layout simulation and sign-off, taking personal ownership of critical blocks. Define and enforce analog design methodologies, simulation corner strategies and layout guidelines, including matching, shielding, guard rings and substrate noise isolation. Drive the analog side of tapeout: own the sign-off checklist, review LVS and DRC results, and coordinate with the digital and layout teams on milestones. Lead silicon bring-up and characterisation of analog blocks: define the bench test plan, debug first-silicon issues, and close the loop between measured behaviour and simulation models. Work with the photonics team on the electrical interfaces to the optical devices, co-optimising for noise, bandwidth and power. Work with the digital ASIC and firmware teams to specify ADC and DAC interfaces, calibration sequences and real-time control requirements. Evaluate and manage the analog EDA toolchain (Cadence Virtuoso, Spectre, Calibre and similar) and maintain or extend the PDK and IP library. Mentor junior and mid-level analog designers, run design reviews, and set the bar for simulation rigour and documentation. What We're Looking For Must-have An MSc or PhD in electronics, microelectronics or a related discipline, or equivalent depth of industrial analog design experience. Eight or more years of hands-on analog or mixed-signal ASIC design, with at least one production-intent or high-volume tapeout as lead designer on one or more critical blocks. Deep expertise in at least one of: TIA or VGA design for optical receivers, high-speed ADC/DAC architectures (SAR, pipeline, sigma-delta), PLL and clock generation, or precision analog (bandgap, LDO, bias). Strong command of the full-custom design flow: schematic capture, transistor-level simulation in Spectre or similar, post-layout extraction, and statistical or Monte Carlo sign-off. Hands-on silicon bring-up and characterisation experience: comfortable at a bench with an oscilloscope, VNA, signal analyser and custom test fixtures. Working knowledge of advanced

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/asic-tech-lead-analog-at-lumai-a611c7

Source: https://jobsbylevel.com/jobs/asic-tech-lead-analog-at-lumai-a611c7

## Cite this page

Level. https://jobsbylevel.com/jobs/asic-tech-lead-analog-at-lumai-a611c7.

Get job alerts: https://jobsbylevel.com/newsletter