# Chassis IP Design Engineer at Intel

Intel is hiring a Chassis IP Design Engineer in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/d6e63f49-ba65-4800-ad14-eae2c86ba78e?utm_medium=ai-agent).

AI Level 1, AI centrality 28 out of 100. India, Bangalore.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 28 out of 100)
- Location: India, Bangalore
- Posted: October 14, 2026
- Apply: https://jobsbylevel.com/go/d6e63f49-ba65-4800-ad14-eae2c86ba78e?utm_medium=ai-agent

## Description

Job Details: Job Description: The Role and Impact As an IP Logic Design Engineer, you will be instrumental in developing and optimizing logic designs for high-performance IP blocks that drive Intel's cutting-edge SoC solutions. Your day-to-day responsibilities will include writing register transfer level (RTL) code, conducting simulations, and ensuring designs meet stringent power, performance, area, and timing goals. You'll play a pivotal role in delivering quality IPs while collaborating across architecture, verification, and SoC integration teams to ensure seamless handoffs and impactful results. Business group The Central Engineering Group (CEG) is Intel's leading innovation hub, focused on designing foundational technologies for integration across Intel's product portfolio. Within this team, the UIC Fabric Design organization specializes in developing reusable IP blocks and subsystems that enhance system-level capabilities. This group contributes to Intel's broader mission of delivering world-class solutions to revolutionize computing across industries. Key Responsibilities - Design and develop RTL code for IP blocks, ensuring functionality, quality, and scalability. - Optimize logic designs to meet power, performance, area, and timing objectives. - Collaborate with architecture teams to define microarchitecture features of IP designs. - Participate in verification plan reviews and implement corrective measures for failing RTL tests. - Support SoC integration teams to ensure high-quality integration and verification of IP blocks. - Work with physical design teams to address timing and implementation challenges. - Drive compliance with quality assurance standards for seamless IP-SoC handoff. Qualifications: Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of experience in state-of-the-art SoC or IP design OR Master's degree with 3+ years of experience. - Proficiency in Verilog/System Verilog, including Lint/CDC/RDC tools and methodologies. - Demonstrated ability to optimize designs for power, performance, and area trade-offs (PPA). Preferred Qualifications - Familiarity with AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols. - Experience in designing IP subsystems, including protocol conversion bridges and debug/trace components. - Understanding of concepts such as QoS, access control, flow control, RAS, and security/error handling. - Proven ability to collaborate across architecture, verification, and SoC integration teams effectively. - Familiarity with using AI tools to assist logic design. - Strong communication skills and experience working with globally distributed teams across time zones. We invite you to join our team, where you'll be empowered to innovate, collaborate, and leave a lasting impact on the future of computing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other

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