# Defect Reduction Engineer at Samsung Electronics

Samsung Electronics is hiring a Defect Reduction Engineer in Austin, United States. It pays $106k-$145k a year and Level rates it Little AI ●○○○; you can [apply on Samsung Electronics](https://jobsbylevel.com/go/ef50dd4a-4bbb-43f5-bf19-f1c30f40ee79?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. 12100 Samsung Blvd, Austin, TX, USA.

## Details

- Company: [Samsung Electronics](https://jobsbylevel.com/companies/samsung-electronics)
- AI level: AI Level 1 (score 0 out of 100)
- Location: 12100 Samsung Blvd, Austin, TX, USA
- Salary: $106k-$145k
- Posted: August 11, 2026
- Apply: https://jobsbylevel.com/go/ef50dd4a-4bbb-43f5-bf19-f1c30f40ee79?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=defect-reduction-engineer-at-samsung-electronics-4944f7

## Prepare for this job

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## Description

About Samsung Austin Semiconductor Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow. Come innovate with us! Position Summary We are seeking a highly skilled and experienced Defect Reduction Engineer to drive yield enhancement and process stability within our advanced semiconductor fabrication environment. This critical role focuses on the identification, analysis, and elimination of defect sources across multiple technology nodes, ranging from legacy production to leading-edge 14nm and foundry processes. The successful candidate will serve as the primary subject matter expert in defectivity, ensuring that our manufacturing processes meet the highest standards of quality and performance. The core of this position involves leading Defect Reduction strategies for New Product Introduction (NPI), where you will independently define inline inspection methodologies and establish robust monitoring plans. You will be responsible for performing deep-dive correlation analyses of tool trend data to identify underperforming equipment and rapidly mitigate process excursions. By leveraging advanced inspection tools (Bright Field, Dark Field, E-beam) and analytical platforms like Klarity, you will trace defects to their root cause and implement permanent corrective actions. Collaboration is central to this role. You will work autonomously yet synchronously with cross-functional teams, including Yield Enhancement (YE), Process Integration (PIE), and Unit Process (UP) engineering, to establish Best Known Methods (BKMs) and drive the reduction of "Single Wafer Low Yield" (SWLY) occurrence. Additionally, you will act as a key technical liaison for foundry customers and support the seamless transfer of new technologies from Samsung HQ in South Korea. The ideal candidate is a self-starter with a minimum of 5 years of semiconductor working experience and a proven track record of solving chronic yield issues in a fast-paced environment. We are looking for a technical leader who can integrate quickly into our operations, manage multiple shifting priorities, and deliver results that directly impact our yield goals and product competitiveness. Role and Responsibilities Here's What You'll Be Responsible For: New Product Introduction (NPI) & Ramp-up Strategic Planning: Serves as the primary representative for defect reduction during NPI, defining how parts will be inspected (strategy & methodology). Setup & Validation: Handles Global Process Management (GPM) setup, conducts specification audits, and performs comparisons to ensure standards are met. Impact Analysis: Evaluates how changes in unit processes or the distribution of parts across different tools (tool spread) affect inline and Non-Product Wafer (NPW) defectivity. Process Monitoring & Root Cause Analysis Trend Analysis: Monitors fab process and tool data to identify "Dog Tools" (underperforming equipment). Excursion Control: Performs correlation analysis to trace defects back to their root cause, enabling rapid response to prevent widespread process excursions. Cross-Functional Collaboratio n Inter-departmental Synergy: Works with Yield Enhancement (YE), Process Integration Engineering (PIE), and Unit Process (UP) teams. Optimization: Evaluates defect data to establish Best Known Methods (BKMs), monitors excursions, and focuses on SWLY (Single Wafer Low Yield) reduction to improve consistency. Technology Node Management FCC Management: Establishes Fail Chip Count (FCC) and trend monitoring plans. Diverse Node Support: Manages a wide range of technology nodes, including: Advanced Nodes: 14nm and Foundry processes, Legacy Nodes: 65nm, 45nm, and 28nm. Operational Support: Leads/supports weekly module meetings to ensure yield and performance targets are achieved. Customer & Global Relations Foundry Service: Acts as a

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