# Design Verification Engineer at Intel

Intel is hiring a Design Verification Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/9503898f-d821-4a9f-9a59-09027c7fc652?utm_medium=ai-agent).

AI Level 1, AI centrality 25 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 25 out of 100)
- Location: US, California, Santa Clara
- Salary: $106k-$149k
- Posted: September 11, 2026
- Apply: https://jobsbylevel.com/go/9503898f-d821-4a9f-9a59-09027c7fc652?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=design-verification-engineer-at-intel-50569f

## Description

Job Details: Job Description: About Intel & Silicon Chassis Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification of next-generation interconnect and chassis IPs that underpin Intel's most ambitious SoC and platform products. Position Overview You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures - developing end-to-end verification skills from day one. We look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work. You do not need to know everything on day one; you do need strong fundamentals, genuine curiosity, and the drive to ramp fast. Key Responsibilities • Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers • Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups • Contribute to functional coverage plans, coverage closure analysis, and regression triage • Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries • Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting • Continuously build depth in hardware design, verification methodology, and the chip development flow What We're Looking For You should demonstrate the following professional traits to be successful: • Genuine curiosity and the drive to ramp fast • Algorithmic thinking with a commitment to writing clean code • Enthusiasm for applying the latest AI-assisted development tools as a core part of how you work Qualifications: This position is not eligible for Intel immigration sponsorship. Minimum Qualifications • BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 3+ months of Internship experience in a hardware design or verification environment • Foundation in logic design and digital circuits - required; ability to read and reason about RTL is essential • Demonstrated algorithmic thinking and software fundamentals application - required • Demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships • Coursework or project exposure to two or more of the following: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, VLSI design • Demonstrated use of AI coding assistants as a regular part of coursework or project work - not occasional use, but as a genuine productivity tool Preferred Qualifications • Coursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar) • Exposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship • Familiarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts • Demonstrated project work (senior design, research, hackathon, personal) involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design • Comfort working in Linux environments, using version control (git), and writing build/test automation scripts • Worked experience in any related field Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy,

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