# Design Verification Engineer at Intel

Intel is hiring a Design Verification Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/e2fd39d5-b5ac-44b2-a8fd-066f0b0dc678?utm_medium=ai-agent).

AI Level 1, AI centrality 23 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 23 out of 100)
- Location: US, California, Santa Clara
- Salary: $106k-$149k
- Posted: November 11, 2026
- Apply: https://jobsbylevel.com/go/e2fd39d5-b5ac-44b2-a8fd-066f0b0dc678?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=design-verification-engineer-at-intel-a9b696

## Description

Job Details: Job Description: About the Team Intel is building a configurable interconnect and chassis generator for SoCs and chiplets, and the Unified Intel Chassis (UIC) team is looking for an Entry Level Design Verification Engineer to be part of it. In this role, you will use simulation, formal verification, and AI-assisted development to check hardware behavior, find bugs, and build reusable verification code. Working closely with architecture, design, and tooling engineers, you will help turn specifications into working, tested hardware. We value strong fundamentals, curiosity, and engineers who follow a problem through to a solution. You will learn by building, testing ideas, and reviewing work with experienced engineers — with room to contribute to models, RTL, and tools as your skills grow. Prior industry experience is not required. Relevant experience may come from coursework, research, internships, or personal projects. Please note: This position is not eligible for Intel immigration sponsorship. Key Responsibilities Develop simulation tests, formal properties, reference models, and checkers for interconnect and chassis IP; learn to select and combine methods for the problem being verified Debug simulation failures and formal counterexamples, distinguish design issues from testbench or assumption errors, and work with the relevant owners to resolve them Translate specifications into verification plans and checks; review assumptions, coverage gaps, and proof results with the team, and take well-scoped features from initial bring-up through verification closure Participate in architecture and design discussions, use models and experiments to clarify behavior and tradeoffs, and contribute reviewed RTL or model changes in collaboration with their owners Build scripts and reusable tools for configuration generation, regression execution, and results analysis across generated designs Use AI-assisted tools in everyday coding, property development, and debugging; review generated work against design intent and validate it with tests and formal analysis rather than accepting the output at face value What We're Looking For You should demonstrate the following professional traits to be successful: Intellectual curiosity and a willingness to ask questions, incorporate feedback, and learn unfamiliar hardware and software concepts A methodical approach to problem-solving — one that distinguishes between what is expected, what is observed, and what needs to be investigated further A collaborative mindset with the ability to communicate clearly and work effectively with engineers across architecture, design, and verification disciplines Qualifications: Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field — with 6+ months of work or academic experience Foundation in digital logic, sequential circuits, and computer architecture, with the ability to read and reason about RTL Programming and algorithmic problem-solving skills, demonstrated in C/C++, Python, or an HDL through coursework, research, projects, or internships Experience explaining expected behavior, devise tests, and investigate unexpected results Hands-on use of AI-assisted development tools in coursework, research, or projects, including reviewing and testing the code they produce All minimum qualifications may be satisfied through internships, academic projects, coursework, or other practical experience. Preferred Qualifications Coursework or project experience with RTL simulation, formal verification, SystemVerilog assertions, or UVM Familiarity with interconnects, cache and memory hierarchies, or protocols such as AXI, CHI, or PCIe Hands-on projects involving RTL design, FPGA implementation, hardware modeling, or hardware-software co-design Experience with Linux, Git, scripting, and automated build or test flows Experience building AI-assisted workflows for specification analysis,

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/design-verification-engineer-at-intel-a9b696

Source: https://jobsbylevel.com/jobs/design-verification-engineer-at-intel-a9b696

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