# Distinguished Hardware Engineer at Cisco

Cisco is hiring a Distinguished Hardware Engineer in San Jose, United States. It pays $285k-$391k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/9227d643-8a63-42be-b1cb-ff1078893f8a?utm_medium=ai-agent).

AI Level 1, AI centrality 26 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 26 out of 100)
- Location: San Jose, California, US
- Salary: $285k-$391k
- Posted: November 2, 2026
- Apply: https://jobsbylevel.com/go/9227d643-8a63-42be-b1cb-ff1078893f8a?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=distinguished-hardware-engineer-at-cisco-189aa1

## Description

The application window is expected to close on: 11/05/2026 Meet the Team The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As a Distinguished Engineer, you will serve as a technical visionary and advisor to Cisco’s engineering business and senior management. You will lead and influence key industry boards, councils, and standards bodies, define and drive the adoption of next-generation technologies, and guide the development of new products and processes. Your expertise will have a broad impact across Cisco’s product portfolio, shaping strategy, research, open-source efforts, and intellectual property development. You will: Drive the long-term technical vision and roadmap for next-generation semiconductor nodes and emerging Angstrom technologies. Strategic Planning : Lead Technology pathfinding and process-design interactions to evaluate futuristic capabilities and quantify technical risks. Risk Management : Drive strategic technology selection and architectural governance under uncertainty to ensure long-tern product viability. Bridge the gap between device physics, architecture, and physical implementation to maximize system efficiency. DTCO Leadership: Pioneer Design-Technology Co-Optimization (DTCO) methodologies to acheive breakthrough gains in Performance, Power, Area, and Cost (PPAC). Advanced Packaging: Architect next Generation 2.5D/3D heterogeneous integration strategies, resolving complex thermal, power, delivery, and signal integrity challenges for large sale AI and networking systems. Influence the external semiconductor and EDA ecosystem to accelerate Cisco's development cycles. EDA Partnership: Collaborate with top-tier EDA vendors to influence tool architecture and co-develop next generation physical design flows for extreme-scale ASICs. Foundry Interlock : Serve as a Primary technical authority in engagements with leading foundries and IP suppliers to steer PDK definitions and silicon rule decks. Flow Convergence: Drive the convergence of custom and automated Place and Route (P&R) flows to close the performance gap in semi-custom digital architectures. Balance aggressive technical targets with business realities and cultivate engineering excellence. TCO Governance : Provide holistic governance balancing microarchitectural performance against manufacturability, yield and Total Cost of Ownership (TCO) . Technical Mentorship : evaluate the global Silicon One engineering organization by mentoring principal engineers and technical leads to foster a culture of innovation. Cross-Functional Partnership : Partner with senior leadership across Architecture, Physical Design, Package and Silicon Operations, as well as external industry standards bodies. Minimum Qualifications Bachelors in Electrical Engineering, Computer Engineering, Microelectronics, Materials Science, or related technical field + 17 years of advanced ASIC/SoC silicon design and physical implementation experience or Masters + 14 years of related experience, or PhD + 10 years of related experience. Experience with technical leadership at the Fellow, Distinguished Engineer, or Chief Architect level, with multi-generation tapeout successes on cutting-edge process nodes (sub-5nm, 3nm, 2nm, or GAA architectures). Experience in Design-Technology Co-Optimization (DTCO), transistor/device physics interactions, standard cell library architecture, and standard

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Source: https://jobsbylevel.com/jobs/distinguished-hardware-engineer-at-cisco-189aa1

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