# E-Core CPU Design Automation Engineer at Intel

AI Level 2, AI centrality 45 out of 100. Malaysia, Penang.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 2 (score 45 out of 100)
- Location: Malaysia, Penang
- Posted: October 7, 2026
- Apply: https://jobsbylevel.com/go/b1ceb8df-2148-4efb-bcd2-30ff8e43d961

## Description

Job Details: Job Description: E-core (formerly known as ATOM), Intel's most efficient CPU Technology team is looking for a highly motivated and technically savvy experienced individual to join our team as Design Automation Engineer. Intel has a vision to create and extend computing technology to connect and enrich the lives of every person. We are designing future generations of high-performance E-core CPUs using the most advanced and innovative process technologies. If you are looking to grow and develop your skillsets while being surrounded by highly motivated and knowledgeable teammates, then this is the organization for you. E-Core CPUs are the industry-leading performance-per-watt CPU that helps: Power the latest Intel laptops, desktops, and high-end gaming platforms. Drive 5G communications by serving as the base station that delivers essential data from your electronic devices across the world at maximum bandwidth. Create Artificial Intelligence (AI) and machine learning devices. Enable a full virtual learning experience for students using the latest Google Chromebooks. As a CPU Physical Design Automation Engineer in the E-core CPU group, you will be responsible for: Developing, debugging, and supporting tools, flows, and methodologies covering backend physical design methodologies and flow automation for high-performance blocks and full chip level using RTL2GDS standard cell level design techniques. Performing analysis of either synthesis, place and route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, power consumption, electrical rule checking, and circuit reliability to identify key issues. Working closely with design teams to understand and debug tool issues and constraints. Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU. Creating documentation and helping with guidelines/specs. Communicating with other team members to solve problems and following solutions through to completion. Excellent verbal and written English communication skills. Leverage AI capabilities to enhance daily operational efficiency and design productivity. Qualifications: Minimum Qualifications Bachelor's Degree in Computer Engineering and/or Electrical/Electronic Engineering and 1+ years of relevant working experience OR Master's Degree in Computer Engineering and/or Electrical/Electronic Engineering Preferred Qualifications 1+ years of experience in VLSI, design automation algorithms, and transistor-level design. 1+ years of experience using industry standard Engineering Design Automation (EDA) VLSI tools/flows from vendors such as Synopsys, Cadence and/or Mentor Graphics for performing synthesis, place-and-route, extraction, timing/power analysis and functional verification. 1+ years' experience with Python, Perl, and/or Tcl scripting languages. 1+ years of relevant working experience in microprocessor or other high speed design backend design. Experience with timing closure methodology for worst-case corner (static timing analysis / STA, statistical variation analysis, spice circuit simulation, ERC, noise analysis flows, cross talk, OCV effects, budget constraints) Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site

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