# Entry Level ASIC/FPGA Design Verification Engineer at Boeing

Boeing is hiring an Entry Level ASIC/FPGA Design Verification Engineer. It pays $79k-$107k a year and Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/6ddcca96-8564-42bd-a19e-f05cd111ef08?utm_medium=ai-agent).

AI Level 1, AI centrality 36 out of 100. USA - El Segundo, CA.

## Details

- Company: [Boeing](https://jobsbylevel.com/companies/boeing)
- AI level: AI Level 1 (score 36 out of 100)
- Location: USA - El Segundo, CA
- Salary: $79k-$107k
- Posted: October 13, 2026
- Apply: https://jobsbylevel.com/go/6ddcca96-8564-42bd-a19e-f05cd111ef08?utm_medium=ai-agent

## Description

Entry Level ASIC/FPGA Design Verification Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Entry Level ASIC/FPGA Design Verification Engineers to join us as part of our Boeing Electronic Products team in El Segundo, CA. Overview Engineers support ASIC, FPGA, or SoC verification activities across advanced aerospace programs including space systems, satellite technologies, communications systems, and related digital subsystems while gaining exposure to broader digital product development activities. Engineers assist in development of electronic architecture and detailed specifications for various electronic products. Assist in development of detailed designs consistent with requirements and specifications. Conduct various methods of testing and analysis to support design. Gather data for technical performance measures. Assist in providing engineering support throughout the lifecycle of the product. Assist with trade studies and literature research to support future product designs. Work under close supervision. Candidates are expected to possess verification fundamentals including simulation concepts, debug methods, coverage approaches, requirements traceability awareness, and general digital verification methodology concepts. Experience with UVM is strongly preferred, and engineers should be prepared to discuss verification fundamentals, SystemVerilog usage, coverage strategy, reusable verification concepts, and their current level of UVM understanding during interviews. Position Responsibilities: Execute assigned verification tasks and progressively increase ownership. Develop simulation, debug, coverage, and requirements traceability skills. Contribute to SystemVerilog and UVM environments, tests, UVCs, and reusable infrastructure. Support integration investigations and system-level debug activities. Contribute to verification objectives, coverage assessments, and closure activities appropriate to experience level. This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location. Basic Qualifications (Required Skills/Experience): This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required. Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement Coursework, Projects, or internship experience with ASIC/FPGA/Soc Design verification Understanding of digital verification fundamentals Experience with SystemVerilog for simulation testbench development and RTL debugging Preferred Qualifications (Desired Skills/Experience): Bachelor’s Degree in Electrical Engineering or Computer Engineering Experience with hardware emulators, especially Palladium Proficiency with hardware verification languages: System Verilog, System Verilog Assertions Ability to executable test plans Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc. Ability to create self-checking and reusable testbenches from scratch Experience developing Functional Coverage Models and Closing Code Coverage Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet) Proficient in scripting languages: Make, Perl, Python, etc. Revision Control Systems: svn, cvs, git Proficient in Linux Environments Familiarity with space-based design techniques and radiation mitigation Demonstrated history of 1st pass success with ASIC designs Conflict of Interest: Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process. Typical Education/Experience: Education/experience typically acquired through advanced technical education from an

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Source: https://jobsbylevel.com/jobs/entry-level-asic-fpga-design-verification-engineer-at-boeing-63b055

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