# Etch Engineer - Process Owner at Samsung Electronics

Samsung Electronics is hiring an Etch Engineer - Process Owner. It pays $102k-$122k a year and Level rates it Little AI ●○○○; you can [apply on Samsung Electronics](https://jobsbylevel.com/go/42856634-59a4-40f0-a74e-56b93ed9daf7?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. 1530 FM 973 Taylor, TX, USA.

## Details

- Company: [Samsung Electronics](https://jobsbylevel.com/companies/samsung-electronics)
- AI level: AI Level 1 (score 0 out of 100)
- Location: 1530 FM 973 Taylor, TX, USA
- Salary: $102k-$122k
- Posted: November 2, 2026
- Apply: https://jobsbylevel.com/go/42856634-59a4-40f0-a74e-56b93ed9daf7?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=etch-engineer-process-owner-at-samsung-electronics-4f9db8

## Prepare for this job

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## Description

About Samsung Austin Semiconductor Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow. Come innovate with us! Position Summary As an Etch Engineer - Process Owner, see roles and responsibilities below. Role and Responsibilities Develop and optimize Front End of Line (FEOL) and Back End of Line (BEOL) plasma etch processes for emerging Gate-All-Around (GAA) architectures including 2 nm node and mature semiconductor technology nodes, including 14nm, 17nm, 28nm FinFET. Implement and sustain Advanced Process Control (APC) methodologies, including feed-forward (FF) process control strategies for trench etch and via-height optimization. Perform Statistical Process Control/Fault Detection and Classification (SPC/FDC) monitoring, statistical yield analysis, and root-cause investigations for plasma etch process excursions, interlocks, and Out-of-Control Action Plan (OCAP) events. Qualify and integrate heterogeneous etch tool platforms, including LAM Research FLEX/KIYO, and/or TEL, Applied Materials, Mattson, PSK and SEMES and cross-platform etch equipment for production deployment. Conduct process matching and technology transfer activities across global semiconductor manufacturing sites. Support factory ramp-up activities through tool qualification planning, capacity optimization, and throughput improvement initiatives. Develop monitoring plans for post-preventive maintenance (PM) defect detection and production wafer qualification. Collaborate with equipment engineering, process integration, metrology, and yield enhancement teams to improve process stability and manufacturing efficiency. Utilize DOE methodologies and statistical analytics platforms, including Spotfire, JMP, Minitab, and Python for process optimization and defect reduction initiatives. Perform failure analysis and material characterization using SEM, EDX, spectroscopy, and related semiconductor characterization techniques. Support semiconductor manufacturing for automotive electronics, memory devices, RF technologies, and advanced display applications. Participate in cost-reduction and risk-assessment initiatives involving process hardware qualification and fab operational efficiency improvements. (Multiple Openings) Skills and Qualifications Bachelor’s degree in Chemical Engineering, Materials Science Engineering, Electrical Engineering, Semiconductor Engineering, or closely related engineering discipline and 24 months of experience in job offered or in a semiconductor plasma etch process engineering role within an advanced-node semiconductor manufacturing environment. Requires 24 months of experience involving the following: 1. Back End of Line (BEOL) and Front End of Line (FEOL) dry plasma etch process development and sustaining; 2. Semiconductor manufacturing using FinFET and/or Gate-All-Around (GAA) process technologies, including Nanosheet 3D transistor technology and Copper to Copper Hybrid Bonding; 3. Statistical Process Control (SPC), Fault Detection and Classification (FDC), Advanced Process Control (APC), and statistical yield analysis methodologies to detect, correct, and optimize semiconductor manufacturing processes to maximize yield; 4. Authorship of critical standard operating procedures (SOPs) for novel etch processes; 5. New Product Introduction: Facilitating launch of new products by optimizing etch recipes and tool spread, and implementing novel APC processes like Feed Forward APC; 6. Semiconductor tool qualification and process matching activities to ensure matching process baselines and hardware to hardware reproducibility; 7. Root-cause analysis for yield excursions and defect reduction; 8. Semiconductor process optimization using Design of Experiments (DOE) methodologies; 9. Semiconductor metrology and characterization, including SEM and EDX analysis; 10. Statistical

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