# Firmware Architect & Subsystem Technical Leader, Acacia at Cisco

Cisco is hiring a Firmware Architect & Subsystem Technical Leader, Acacia. It pays $192k-$276k a year and Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/b98ffa2f-f289-4724-9600-fefdf8c8f09e?utm_medium=ai-agent).

AI Level 1, AI centrality 32 out of 100. Maynard, Massachusetts, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 32 out of 100)
- Location: Maynard, Massachusetts, US
- Salary: $192k-$276k
- Posted: October 21, 2026
- Apply: https://jobsbylevel.com/go/b98ffa2f-f289-4724-9600-fefdf8c8f09e?utm_medium=ai-agent

## Description

Meet the Team Acacia (part of Cisco) is the industry market leader and pioneer in high-speed coherent optical transceivers and pluggable optical interconnects. Acacia’s groundbreaking coherent optical solutions are deployed across all hyperscaler cloud providers and telecommunications networks, interconnecting data centers across metropolitan spans, thousands of kilometers of terrestrial fiber, and deep submarine links. With the explosive growth of artificial intelligence and machine learning workloads driving unprecedented bandwidth requirements, Acacia products are expanding into data center fabrics and high-performance compute clusters. In addition to powering deep-space optical communication systems, Acacia leads the client-side optics market with breakthrough PAM4 DSP architectures, including 1.6T PAM4 DSP platforms. Joining Acacia’s Software team means collaborating with world-class engineers to push boundaries of optical networking. Your Impact As an Embedded Software Engineering Technical Leader for this team, you will serve as a principal firmware architect guiding the embedded CPU software architecture that configures, manages, and optimizes Acacia’s transceiver subsystems and future System-on-Chip (SOC) architectures. In this high-impact technical leadership role, you will: Lead end-to-end architecture, design, and implementation of high-reliability, low-latency embedded firmware for multi-core microcontrollers (ARM Cortex-R and Cortex-M). Partner directly with ASIC, DSP, Optical, and Hardware Engineering architects to co-design hardware/software interfaces, configure complex optical subsystems, and resolve critical hardware-software boundary challenges. Architect robust multi-threaded control-plane firmware, Board Support Packages (BSPs), device drivers, and real-time state machines on bare-metal and RTOS platforms. Establish best-in-class firmware engineering standards, mentor senior and intermediate engineers across the software organization, and drive multi-functional alignment from high-level system modeling down to low-level register and bit-level implementation. Provide technical direction and intermediate leadership runway to help scale our growing engineering presence in the community. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 12+ years of professional experience to include: 10+ years in low-level embedded C and C++ programming for resource-constrained hardware environments. 8+ years architecting and developing real-time embedded firmware on bare-metal systems and real-time operating systems (RTOS such as VxWorks, FreeRTOS, ThreadX, or similar). Experience crafting lfirmware for ARM processors/microcontrollers (such as ARM Cortex-M or Cortex-R cores), including BSPs, device drivers and hardware peripheral interfaces (I2C, SPI, UART, MDIO). Ability to work 100% onsite in Maynard, MA during the initial one-year onboarding period (with hybrid flexibility available thereafter). Preferred Qualifications Firmware architecture for optical transceivers, high-speed mixed-signal ICs, photonics, or telecommunications transmission hardware. Development of control-plane software, state machines, and multi-processor/multithreaded communication protocols. Successful leadership of firmware engineering projects and collaborating across ASIC design, DSP modeling, Hardware, and SQA teams. Proficiency with modern version control and CI/CD tools (Git, Jira, Perforce) and automation scripting (Python, Shell). Experience in semiconductor/hardware environments or engagement with optical industry standards bodies (e.g., OIF, IEEE). Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/firmware-architect-subsystem-technical-leader-acacia-at-cisco-c44878

Source: https://jobsbylevel.com/jobs/firmware-architect-subsystem-technical-leader-acacia-at-cisco-c44878

## Cite this page

Level. https://jobsbylevel.com/jobs/firmware-architect-subsystem-technical-leader-acacia-at-cisco-c44878.

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