# GPU Logic Design Engineer at Intel

Intel is hiring a GPU Logic Design Engineer in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/208488c6-0d20-4954-893b-e75a9a9b2c77?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. India, Bangalore.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: India, Bangalore
- Posted: October 29, 2026
- Apply: https://jobsbylevel.com/go/208488c6-0d20-4954-893b-e75a9a9b2c77?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=gpu-logic-design-engineer-at-intel-fbd227

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## Description

Job Details: Job Description: The Role and Impact As a DFT Design Engineer, you will play a crucial role in developing and delivering high-quality design-for-test (DFT) solutions for cutting-edge semiconductor products. You will focus on logic design, RTL coding, and simulation, while collaborating on architecture and microarchitecture definitions. Your contributions directly impact product quality and manufacturability by optimizing test coverage, debug efficiency, and production ramp-up, ensuring Intel's leadership in advanced SoC designs. Business group The Data Center Group (DCG) drives innovation in data center technologies to empower businesses and industries globally. As part of this high-impact organization, you will contribute to the development of world-class systems and solutions that support Intel's vision to transform data into actionable insights, enabling scalable, efficient, and secure computing. Key Responsibilities - Develop logic design, RTL coding, and DFT timing closure support for test content generation, including SCAN, MBIST, and BSCAN. - Collaborate on the definition of architecture and microarchitecture features for blocks and subsystems under DFT design. - Create and optimize HVM content for rapid bring-up and production ramp on automatic test equipment (ATE). - Apply strategies, tools, and methods to integrate DFT into RTL and structural code while meeting power, performance, area, and timing goals. - Review verification plans and drive verification of DFT designs to ensure alignment with architecture and microarchitecture specifications. - Resolve RTL test failures and implement corrective measures to ensure design accuracy and feature correctness. - Integrate DFT blocks into functional IP and SoC, supporting SoC customers to ensure seamless integration and high-quality design outcomes. - Collaborate with post-silicon and manufacturing teams to support debug and verification on silicon, documenting learnings for continuous improvement. - Drive high test coverage and develop structural and specific IP tests to achieve quality and defect-per-million (DPM) objectives. Qualifications: Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 0-1 years of hands-on experience through internships, academic projects, coursework, or training. - OR a Master's degree in Electrical Engineering, Computer Engineering, or related field with no prior professional experience. - Proficiency in RTL coding and simulation tools (e.g., SystemVerilog, VCS). - Foundational understanding of DFT methodologies such as SCAN, MBIST, and BSCAN. Preferred Qualifications - Strong problem-solving skills and a collaborative mindset. - Familiarity with SoC architecture and microarchitecture features. - Knowledge of test equipment tools and strategies for production ramp-up. - Passion for innovation and commitment to delivering high-quality solutions. Join us in shaping the future of semiconductor technology. Your contributions will drive the scalability and reliability of Intel's products, while fostering personal growth and career development in an inspiring environment. Job Type: College Grad Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or

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