# HPC System Architecture at Intel

AI Level 1, AI centrality 0 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: US, California, Santa Clara
- Salary: $221k-$312k
- Posted: October 6, 2026
- Apply: https://jobsbylevel.com/go/db193e58-6551-46da-a291-d5d6c70ecbc5

## Description

Job Details: Job Description: The HPC System Architect is the senior technical lead responsible for defining the next generation of Intel's leading-edge high-performance computing systems. Reporting directly to Nic Dube, Corporate Vice President and General Manager of Data Center Systems and Solutions, this position owns forward-looking HPC system architecture from concept through committed definition. You will work directly with Intel's CPU and GPU teams to architect the systems that follow today's products - shaping silicon requirements, and defining system-level architecture for the large-scale, scale-out clusters that characterize production HPC. The role spans full-system definition: compute node design, memory and I/O balance, scale-out fabric and topology, and the software stack that determines delivered application performance at scale. You will engage directly with the customers that set the leading edge of HPC - DOE national laboratories and their exascale and post-exascale programs, financial services institutions, oil and gas operators, and major academic and government research computing centers - translating their workload and facility requirements into system architectures Intel can build, and Intel's roadmap into system concepts they can commit to. Responsibilities Own system-level architecture for next-generation HPC clusters: node definition, CPU and GPU configuration, memory bandwidth-to-capacity balance, I/O and parallel storage architecture, and scale-out fabric and topology. Define scale-out interconnect architecture - fabric selection, network topology, bisection bandwidth and blocking ratios, collective and communication performance, and resilience at thousands-of-node scale. Partner with the CPU and GPU teams to define product requirements for future HPC systems, bringing system-level and workload evidence into silicon definition while requirements remain open. Build performance models that project delivered application throughput at scale on unreleased silicon and use them to drive configuration and roadmap decisions. Lead architecture co-design and benchmark definition with leadership HPC customers, including acceptance criteria for standard and customer-proprietary application suites. Drive HPC requirements into Intel's CPU, GPU, platform, and software roadmaps across DCG and the product and design organizations. Evaluate emerging technologies for next-generation HPC systems, including advanced memory, Ultra Ethernet and other scale-out fabric standards, optical interconnect, and heterogeneous accelerator integration. Produce reference architectures and system specifications that platform teams, OEM and ODM partners, and system integrators can build to. Grow and lead HPC architecture capability within the team, providing technical direction and mentorship to architects and engineers. Successful Candidate Profile Deep expertise in HPC system architecture at cluster scale, spanning CPU and GPU configuration, memory subsystem design, scale-out interconnect, and parallel storage. Demonstrated experience defining systems around unreleased silicon and influencing CPU or accelerator requirements from a system and workload perspective. Fluency with HPC workload characteristics and performance analysis, including quantitative reasoning about scaling behavior, communication patterns, and bottlenecks at scale. Working knowledge of the HPC software stack - MPI, OpenMP, GPU programming models, schedulers, and math and communication libraries. Proven credibility with sophisticated technical customers in high-stakes procurement and co-design settings. Strong understanding of the competitive HPC landscape, including alternative CPU and accelerator architectures, fabric options, and system vendor positioning. Excellent written and oral communication skills, effective with both deep technical audiences and executive stakeholders. Comfort with high ambiguity and a track record of driving clarity in undefined

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