# Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years at Cisco

Cisco is hiring a Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/476a300c-dd4c-41f4-bf36-c7c4b3305cf7?utm_medium=ai-agent).

AI Level 1, AI centrality 10 out of 100. Bangalore, India.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 10 out of 100)
- Location: Bangalore, India
- Posted: September 17, 2026
- Apply: https://jobsbylevel.com/go/476a300c-dd4c-41f4-bf36-c7c4b3305cf7?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=leader-manager-asic-design-verification-engineering-verilog-uvm-testbench-technical-leadership-hardware-emulation-soc-exp-15-years-at-cisco-ef4abf

## Prepare for this job

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## Description

Meet the Team Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System Verilog and UVM methodology with in-depth knowledge of C++, scripting as well as ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Leads ASIC engineering teams to deliver high-performance, high quality and reliable ASICs for Cisco's diverse product platforms. Leads teams in defining and verifying ASICs and ASIC subsystems to ensure alignment with stringent quality requirements for deployment across Cisco’s platforms. Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality. Collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up. Defining and Building UVM/System Verilog testbenches from scratch or enhancing existing testbenches with focus on reuse Defining new DV methodologies or enhancing the existing methodologies In-depth understanding of the architecture, and identification of problems and solutions. End-to-end verification of one or more design blocks simultaneously while helping full chip team with integration and support. Test plan generation, review, planning and execution, meeting all criteria of ASIC group. Help in developing Emulation infrastructure using C/C++, that has to work with UVM based verification environment. Gate level simulation and SDF back annotation for blocks as part of pre-silicon verification. Code and Functional coverage-based simulation run, coverage collection, merging and working with designers to fill coverage holes. Participating in all phases during ASIC development – RTL Verification, Emulation and post-silicon validation Recommending best practice, identifying and suggesting innovative solutions to improve efficiency and quality Leading and mentoring team of junior engineers in addition to the assigned task. Strong focus on efficiency, quality, reusability. Drives design verification solutions across the business. Ensure culture of code reviews and postmortems. Act as the design verification leader, owning and leading all the above aspects, including driving the technical decisions made at the program level with rest of the dv teams, conducting weekly dv meetings, sync-ups with stake holders and cross functional teams like Architecture, Design, Emulation, SW, PSV. Minimum Qualifications BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC. Have led a design team for a minimum of 5+ years Must have prior experience of developing UVM based infrastructure from scratch in more than one projects. Ability to handle complex features/parts of chip independently. Quick learner must be able to work in a fast pace dynamic environment and must be able to deliver quality even in aggressive schedule. Strong teamwork quality – must be able to work in a highly collaborative team. Overseeing reusability, comes up reusable solution to improve efficiency. Must always focus on efficiency and quality. Ability to build, lead and mentor a team of engineers and ensuring quality delivery as a team. Proficient in merging and analyzing code coverage data generated functional simulation Good working knowledge in C,

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Source: https://jobsbylevel.com/jobs/leader-manager-asic-design-verification-engineering-verilog-uvm-testbench-technical-leadership-hardware-emulation-soc-exp-15-years-at-cisco-ef4abf

## Cite this page

Level. https://jobsbylevel.com/jobs/leader-manager-asic-design-verification-engineering-verilog-uvm-testbench-technical-leadership-hardware-emulation-soc-exp-15-years-at-cisco-ef4abf.

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