# Manager, Project Management - Chip Design at NVIDIA

NVIDIA is hiring a Manager, Project Management - Chip Design in Tel Aviv, Israel. Level rates it Little AI ●○○○; you can [apply on NVIDIA](https://jobsbylevel.com/go/97a35854-0245-426e-8698-0a08f0ad6e13?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. Israel, Tel Aviv.

## Details

- Company: [NVIDIA](https://jobsbylevel.com/companies/nvidia)
- AI level: AI Level 1 (score 0 out of 100)
- Location: Israel, Tel Aviv
- Posted: September 15, 2026
- Apply: https://jobsbylevel.com/go/97a35854-0245-426e-8698-0a08f0ad6e13?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=manager-project-management-chip-design-at-nvidia-bbe514

## Prepare for this job

The job page lists 3 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/manager-project-management-chip-design-at-nvidia-bbe514

## Description

NVIDIA's Switch ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development of NVIDIA's most advanced and complex switch ASICs — from concept to tape-out — and drive the chip through power-on and qualification to production release. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams. What you'll be doing: Development Management: Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out. Post-Silicon Execution: Drive chip power-on, bring-up, and qualification to production release. Execution Plans: Define and implement execution plans in collaboration with cross-discipline leaders in unit-level, full-chip, physical design, and firmware/software emulation. Roadmap Definition: Contribute to the definition of NVIDIA's switch ASIC roadmap. What we need to see: BS or MS in Computer or Electrical Engineering, or equivalent experience. 10+ overall years of experience in chip design. 5+ years of chip design/verification management experience as a second- or third-level manager, leading organizations of 50+ engineers. Proficiency in RTL design (Verilog), verification (UVM, SystemVerilog), System-On-Chip design/integration flow, and design automation. Strong system view with the ability to collaborate across multiple interfaces. Strong analytical and problem-solving skills. Excellent communication and teamwork abilities. Experience in synthesis and physical design is a plus.

Source: https://jobsbylevel.com/jobs/manager-project-management-chip-design-at-nvidia-bbe514

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