# Memory Electrical Validation Engineer at Intel

Intel is hiring a Memory Electrical Validation Engineer. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/2059076f-4086-460c-94ea-4570fdd49601?utm_medium=ai-agent).

AI Level 1, AI centrality 34 out of 100. Malaysia, Penang.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 34 out of 100)
- Location: Malaysia, Penang
- Posted: November 13, 2026
- Apply: https://jobsbylevel.com/go/2059076f-4086-460c-94ea-4570fdd49601?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=memory-electrical-validation-engineer-at-intel-59105b

## Description

Job Details: Job Description: At Intel, innovation starts with you. We are pushing the limits of silicon, AI, and edge-to-cloud architecture to power breakthrough technologies worldwide. Here, your skills will drive meaningful impact, solving real-world challenges and defining the next era of tech. Join our team and lead the future of engineering. Join Intel's Memory Validation Team as a Memory Electrical Validation Engineer, where you will serve as a technical expert and lead validator for cutting-edge memory technologies embedded in mobile and desktop CPU products. In this role, you will be responsible for leading the electrical validation strategy, signal integrity compliance, and system margin analysis for Intel's memory interfaces. You will drive complex post-silicon debug, refine Memory Reference Code (MRC) requirements, and collaborate closely with cross-functional design, architecture, and firmware teams to ensure robust product quality, high-volume production readiness, and optimal silicon performance. Key Responsibilities: Electrical Validation Strategy Execution Lead Validation Execution: Define, own, and execute comprehensive electrical validation (EV) test strategies and plans for high-speed memory I/O interfaces to achieve aggressive performance, quality, and production goals. Signal Integrity /System Margin: Validate analog circuit performance, signal integrity compliance (SIV/SMV), and system-level electrical margins across temperature, voltage, and process corners to ensure stable operation. Test Infrastructure / Automation: Design, execute, and continuously optimize validation procedures, specialized test automation frameworks, and system margin analysis tooling. Post-Silicon Debug / Design Collaboration Complex Failure Triage: Drive deep-dive debug for electrical design features, identifying root causes for functional, parametric, and triage failures. Lead DOEs: Formulate and execute multi-variable Design of Experiments (DOEs) in close collaboration with circuit design, logic, and pre-silicon teams to drive silicon issues to resolution. I/O Interaction Testing: Characterize complex interactions between electrical design elements, board-level environments, and silicon features using post-silicon validation infrastructure. Firmware Optimization/Cross-Functional Alignment MRC Analysis / Tuning: Analyze, refine, and optimize Memory Reference Code (MRC) steps, calibration values, and firmware algorithms for margin, power, and quality improvements. Cross-Team Integration: Collaborate directly with architecture, circuit design, pre-silicon verification, and system integration teams to ensure robust validation coverage across the entire memory subsystem. Technical Guidance: Provide technical direction and mentorship to junior validation engineers on validation methodologies and debug techniques. Qualifications: Minimum Qualifications Education / Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of industry experience, OR Master's degree with 4+ years of industry experience, OR PhD with 2+ years of industry experience. Core Technical Experience (Must meet all): 4+ years of hands-on experience in memory electrical validation, including Signal Integrity Validation (SIV) and Signal Margin Validation (SMV). 4+ years of experience in analog/mixed-signal circuit fundamentals, electrical calibration methodologies, and post-silicon memory validation/debug processes. Solid functional knowledge of Memory Reference Code (MRC) firmware execution paths, parameters, and debug flows for root-cause analysis. Preferred Qualifications 6+ years of experience in high-speed mixed-signal IP electrical validation, high-speed I/O characterization, or signal integrity (SI/PI) analysis. Deep domain experience with modern high-speed memory technologies (e.g., DDR5, LPDDR5/5X, LPDDR6) and JEDEC interface specifications. Proven track record of leading complex root-cause debug

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/memory-electrical-validation-engineer-at-intel-59105b

Source: https://jobsbylevel.com/jobs/memory-electrical-validation-engineer-at-intel-59105b

## Cite this page

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