# Photonic IC Design Engineer, Chip-to-System Integration at K2 Space

K2 Space is hiring a Photonic IC Design Engineer, Chip-to-System Integration in Seattle, United States. It pays $130k-$200k a year and Level rates it Little AI ●○○○; you can [apply on K2 Space](https://jobsbylevel.com/go/54f842c6-9273-4cd1-8670-4596228c53ac?utm_medium=ai-agent).

AI Level 1, AI centrality 32 out of 100. Seattle, WA.

## Details

- Company: [K2 Space](https://jobsbylevel.com/companies/k2-space)
- AI level: AI Level 1 (score 32 out of 100)
- Location: Seattle, WA
- Salary: $130k-$200k
- Posted: October 23, 2026
- Apply: https://jobsbylevel.com/go/54f842c6-9273-4cd1-8670-4596228c53ac?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=photonic-ic-design-engineer-chip-to-system-integration-at-k2-space-3a95f1

## Description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply. The Role K2's ambitions extend beyond the satellite bus. By designing and operating our own spacecraft and regularly manifesting hardware to orbit, K2 is uniquely positioned to develop, test, and deploy ambitious, “limit-of-physics” optical and photonic payloads across MEO, GEO, cislunar, and deep space on unprecedented timelines. The satellite bus is the platform – the payloads are the mission. As a Photonic IC Design Engineer focused on chip-to-system integration, you will design photonic integrated circuits (PICs) and the packages that connect them to the outside world: small, light, low-cost, and rugged enough to fly at constellation scale. You will own the boundary between chip and system on both sides: optically, how light gets on and off the chip and how fibers are attached and held; electrically, the high-speed modulators, RF interfaces, and bias and tuning control that connect the PIC to its drive electronics. You will also make sure the whole assembly survives launch and years in orbit. Your coupling-loss, modulator, and bandwidth numbers feed directly into system link budgets, so you will work closely with K2's systems, photonics test and automation, RF, ASIC, and manufacturing teams, and with external foundry and packaging partners. As a founding member of the photonics team, you will help set how K2 designs, packages, and qualifies photonic hardware. Responsibilities Design, simulate, and lay out PIC devices and circuits (edge and grating couplers, spot-size converters, photodetectors, and passive components) from specification to tapeout on commercial integrated photonics foundry platforms. Design high-speed modulators (e.g., traveling-wave Mach-Zehnder and ring modulators), including electrodes, terminations, and RF launches, and co-design them with RF and ASIC engineers against driver and TIA specifications. Implement bias and tuning control in hardware: place heaters and monitor photodiodes, define the drive and readout interface with K2's electronics engineers, and bring up closed-loop modulator bias and resonator locking, verified over temperature and radiation. Set the optical I/O requirements (coupling loss, alignment tolerance, polarization, and I/O placement on the die) and work them into the floorplan with chip designers and into the link budget with systems engineers. Design the mechanical side of the package in 3D CAD: PIC carriers and submounts, fiber-array V-groove and lid geometry, strain relief, and alignment and assembly fixtures, with tolerance stack-ups tied back to the coupling-loss budget. Drive radiation, thermal-vacuum, and vibration qualification of photonic devices and

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/photonic-ic-design-engineer-chip-to-system-integration-at-k2-space-3a95f1

Source: https://jobsbylevel.com/jobs/photonic-ic-design-engineer-chip-to-system-integration-at-k2-space-3a95f1

## Cite this page

Level. https://jobsbylevel.com/jobs/photonic-ic-design-engineer-chip-to-system-integration-at-k2-space-3a95f1.

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