# Physical Design Automation Engineer at Intel

Intel is hiring a Physical Design Automation Engineer in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/1ec393e0-9252-487c-92c6-c75785ec5cc1?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. India, Bangalore.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: India, Bangalore
- Posted: October 27, 2026
- Apply: https://jobsbylevel.com/go/1ec393e0-9252-487c-92c6-c75785ec5cc1?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=physical-design-automation-engineer-at-intel-7ddc02

## Prepare for this job

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## Description

Job Details: Job Description: The Design Technology Platform team at Intel Foundry India is chartered with process technology definition, advanced methodology development, and design prototyping on Intel's latest process nodes. We support Intel's internal and external design customers and offer a unique opportunity to be among the first engineers working on cutting-edge process technologies. We are seeking an experienced Technical Lead - APR Design Automation to develop and optimize RTL-to-GDS (R2G) flows primarily using Cadence Innovus Implementation System, while supporting test chip and foundry IP needs. The ideal candidate will bring deep expertise in Cadence Innovus-based PnR flow development, with working knowledge of Synopsys Fusion Compiler being a strong added advantage. A key aspect of this role will be enabling, deploying, and supporting Cadence Innovus-based APR flows for Intel's internal product design teams as well as external foundry customers who are leveraging Intel's process technology - ensuring robust, scalable, and production-ready flow solutions that meet the design and performance requirements across a diverse customer base. This is an individual contributor (IC) technical leadership role focused on physical design automation tools, flows, and methodologies on leading-edge process nodes. • Lead the development, deployment, and continuous improvement of RTL-to-GDS flows using Cadence Innovus as the primary PnR platform • Define and drive physical design tools, flows, and methodologies including: o Block-level implementation and integration o Floorplanning, placement, CTS, and routing automation o Timing closure methodologies • Develop and maintain Tcl-based scripting and automation to enhance layout productivity within Innovus and related Cadence tools • Evaluate and benchmark Cadence Innovus vs. Synopsys Fusion Compiler flows; provide data-driven recommendations on tool and methodology selection • Enable and support industry-standard static timing analysis (STA) tools for test chips and Foundry IPs (FIPs), and ensure continued support and enhancement • Collaborate with central CAD, design teams, local CAD teams, and EDA vendors (Cadence, Synopsys) to define next-generation PnR methodologies • Work closely with internal and external design customers to understand requirements and deliver robust, scalable automation solutions • Respond to customer/client requests proactively, developing solutions leveraging formal expertise and engineering judgment • Contribute to process node bring-up by validating and refining flows on Intel's latest technology nodes Qualifications: Educational Requirements Master's degree in M.Tech or MS in Microelectronics, Electronics Engineering, or an equivalent qualification from a reputed institute, with relevant industry experience in physical design and APR flow development Technical Qualifications Physical Design and APR Expertise Proven hands-on experience in block-level design closure using Cadence Innovus Implementation System as the primary APR tool for end-to-end RTL-to-GDS flows Strong working knowledge of all key physical design stages including Floorplanning covering die size estimation, macro placement and pin assignment, Power Planning covering power grid design, IR drop awareness, ring and stripe strategies, Placement covering timing-driven and congestion-aware placement optimization, Clock Tree Synthesis covering clock tree design, skew and latency optimization, and Routing covering global and detailed routing and DRC-clean routing closure Well-versed with multiple optimization techniques available in Cadence Innovus for achieving design closure, including timing, area, power, and congestion optimizations Ability to guide and mentor the team in resolving complex implementation challenges and providing structured solutions Timing and Constraints Strong understanding of digital timing concepts including setup, hold, clock domain crossing CDC, and multi-mode

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