# Physical Design Clocking Engineer at Intel

Intel is hiring a Physical Design Clocking Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/2c06bcd5-b333-4060-ae88-a9211c0eefdf?utm_medium=ai-agent).

AI Level 1, AI centrality 36 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 36 out of 100)
- Location: US, California, Santa Clara
- Salary: $106k-$149k
- Posted: November 3, 2026
- Apply: https://jobsbylevel.com/go/2c06bcd5-b333-4060-ae88-a9211c0eefdf?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=physical-design-clocking-engineer-at-intel-4e476a

## Description

Job Details: Job Description: As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming RTL to GDS to produce design databases ready for manufacturing. On a day-to-day basis, you will execute various aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. Your work will directly contribute to optimizing design parameters such as power, frequency, and area, impacting Intel's product innovation and delivery. You will be part of the Data Center Group (DCG), a business unit focused on developing innovative solutions that power the future of computing. DCG works on designing advanced technologies for data centers, cloud services, and high-performance computing environments, enabling Intel's broader mission to shape the future of technology. This team provides a collaborative environment driven by technical excellence and a passion for innovation. The primary responsibilities for this role will include, but are not limited to: Conduct physical design implementation tasks, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. Perform verification and signoff activities, such as equivalence verification, reliability verification, layout verification, and structural design checking. Analyze results and provide recommendations to resolve violations for current and future architectures. Optimize designs to improve product level parameters, including power, frequency, and area. - Participate in developing and enhancing physical design methodologies, flows, and automation processes. Utilize industry-standard EDA tools to execute and validate physical design processes effectively. Qualifications: Minimum Qualifications : Minimum qualifications are required to be initially considered for this position. Bachelor's degree in a relevant field with 0-1 years of hands-on experience in physical design, demonstrating skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in a relevant field with no prior professional experience. Proficiency in physical design tools, such as synthesis, place and route, and timing analysis software. Familiarity with EDA tools and methodologies used in physical design and verification workflows. Preferred Qualifications: Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Strong analytical and problem-solving skills to identify and resolve design violations effectively. Excellent communication and collaboration abilities to contribute within a dynamic team environment. A proactive mindset and eagerness to learn and improve physical design methodologies and flows. Join us in shaping the future of data-centric technology by applying your skills, curiosity, and passion for innovation. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD The range displayed on this job posting reflects the minimum and

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Source: https://jobsbylevel.com/jobs/physical-design-clocking-engineer-at-intel-4e476a

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