# Physical Design Technical Leader | ASIC/SoC physical design at Cisco

Cisco is hiring a Physical Design Technical Leader | ASIC/SoC physical design in Pune, India. Level rates it Little AI ●○○○; you can [apply on Cisco](https://jobsbylevel.com/go/35517123-f5d5-4013-925d-57c8d20cfe32?utm_medium=ai-agent).

AI Level 1, AI centrality 37 out of 100. Pune, India.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 37 out of 100)
- Location: Pune, India
- Posted: November 13, 2026
- Apply: https://jobsbylevel.com/go/35517123-f5d5-4013-925d-57c8d20cfe32?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=physical-design-technical-leader-asic-soc-physical-design-at-cisco-024c07

## Description

Meet the Team Cisco’s Silicon One Optics Group (S1O) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping S1O’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. Your Impact We are seeking an experienced Physical Design Technical Leader to guide our engineering team and drive physical implementation for Cisco's next-generation silicon photonics driver and receiver ICs, powering 100G, 200G, and 400G-per-lambda Co-Packaged Optics (CPO) and optical engine solutions. In this high-impact role, you will lead the physical design strategy and execution for high-performance silicon integrating sophisticated digital control logic, CPU subsystems, high-speed standard interfaces (UCIe), and ultra-fast transmit/receive data-paths in groundbreaking process nodes (TSMC sub-5nm/3nm/2nm). As a Technical Leader, you will own block-level and full-chip physical implementation from synthesis through final tape-out (TO) while advising, mentoring, and scaling a team of physical design engineers. You will establish advanced physical design methodologies, drive floor-planning, place & route, low-skew clock and power distribution, multi-corner timing closure (STA), EM/IR integrity, and DRC/LVS physical verification sign-off. Additionally, you will partner closely with Architecture, Analog Front-End, Layout, and Photonic packaging teams to ensure first-pass silicon success and drive breakthrough execution across the complete product lifecycle from concept to production. Technical & People Leadership : Lead, mentor, and technically steer a team of physical design engineers, driving task allocations, schedule tracking, and design reviews. Full-Flow Ownership : Own full-chip and hierarchical block-level RTL-to-GDSII implementation and sign-off on advanced nodes. Methodology & Flow Innovation: Architect robust, automated backend flows (Innovus / Fusion Compiler, Pegasus / Calibre, Voltus / RedHawk) to boost team productivity and tapeout predictability. Multi-functional Collaboration: Serve as the primary physical design communicate with Analog Design, Custom Layout, Package Co-Design, and Foundry partners. Minimum Qualifications Bachelor’s degree or equivalent experience in electrical engineering, Electronics & Communication or related field with minimum 12+ years of Industry experience 8+ years of physical design (PD) experience delivering ASIC/SoC designs in sophisticated CMOS technology nodes (7nm/5nm/3nm/2nm) Proven experience driving the full RTL-to-GDSII flow at block and/or full-chip level-including hierarchical floor-planning, power grid design, place & route (P&R), clock tree synthesis (CTS), timing closure, and physical verification sign-off. Strong proficiency with industry-standard EDA tools (Innovus/ICC2/Fusion, Tempus/PrimeTime, Voltus/RedHawk, Calibre/Pegasus etc.) Strong scripting proficiency in Tcl, Python, Bash, or Perl for flow automation, quality of results (QoR) tracking, and efficiency improvements Ability to lead a team of PD engineers & work collaboratively with globally dispersed multi-functional teams Preferred

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/physical-design-technical-leader-asic-soc-physical-design-at-cisco-024c07

Source: https://jobsbylevel.com/jobs/physical-design-technical-leader-asic-soc-physical-design-at-cisco-024c07

## Cite this page

Level. https://jobsbylevel.com/jobs/physical-design-technical-leader-asic-soc-physical-design-at-cisco-024c07.

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