# Platform Signal/Power Integrity Engineer Lead at Intel

Intel is hiring a Platform Signal/Power Integrity Engineer Lead. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/e47e5c79-59d5-4b17-b9a4-8955ccd8603a?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. Malaysia, Penang.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: Malaysia, Penang
- Posted: October 27, 2026
- Apply: https://jobsbylevel.com/go/e47e5c79-59d5-4b17-b9a4-8955ccd8603a?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=platform-signal-power-integrity-engineer-lead-at-intel-fec377

## Prepare for this job

The job page lists 2 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/platform-signal-power-integrity-engineer-lead-at-intel-fec377

## Description

Job Details: Job Description: Job summary The Platform Signal/Power Integrity (SI/PI) Engineer Lead is responsible for defining, developing, and delivering Signal Integrity and Power Integrity solutions for Intel next-generation validation and product platforms. The role provides technical leadership in platform electrical architecture, high-speed interface implementation, schematic design, PCB layout review, routing guideline development, simulation, validation, and debugging activities. The successful candidate will collaborate closely with silicon, package, platform design, PCB layout, firmware, validation, and manufacturing teams to ensure high-performance, robust, and reliable platform designs that meet electrical, timing, signal quality, and power delivery requirements. Key Responsibilities: • Lead Signal Integrity and Power Integrity activities for complex platform, board, and package designs. • Perform pre-layout and post-layout SI/PI simulations and analysis. • Analyze and optimize: Channel loss Reflection Crosstalk Jitter Timing margin Power delivery network (PDN) performance Power noise and voltage droop • Develop electrical budgets and design margin requirements for high-speed interfaces. • Correlate simulation results with laboratory measurements and validation data. • Drive platform electrical architecture and implementation reviews. • Perform schematic capture and detailed schematic reviews for complex validation and production platforms. • Review power architecture, voltage regulator implementation, termination schemes, and interface connectivity. • Define stack-up, impedance, return path, and power distribution requirements. • Ensure compliance with platform electrical specifications and design targets. • Develop and maintain PCB design guidelines and routing constraints. • Define routing requirements for high-speed interfaces including: DDR4/DDR5 PCIe Gen4/Gen5/Gen6 USB4/Thunderbolt Ethernet CXL High-speed SerDes links • Conduct PCB layout reviews and provide sign-off recommendations. • Drive implementation reviews for: Length matching Differential pair routing Reference plane transitions Via optimization Return path continuity Decoupling placement EMI-sensitive routing practices • Work closely with PCB layout engineers and board vendors to resolve implementation issues. • Generate and maintain platform SI/PI design guidelines. • Develop interface-specific routing recommendations and implementation specifications. • Document design rules, characterization reports, simulation methodologies, and lessons learned. • Create customer-facing and internal SI/PI collateral supporting platform development and deployment. • Develop validation methodologies and compliance testing plans. • Perform electrical characterization and measurements using: Oscilloscopes Vector Network Analyzers (VNA) TDR/TDT equipment Logic analyzers Protocol analyzers • Debug signal integrity, timing, and power delivery failures. • Lead root-cause analysis and corrective action activities during board bring-up and validation. • Lead SI/PI reviews across multiple platform programs. • Mentor engineers in SI/PI methodology, PCB design practices, and debugging techniques. • Drive best practices and continuous improvement initiatives. • Provide technical leadership across platform, silicon, package, and validation organizations. Qualifications: Minimum Qualifications • Bachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. • 9+ years of experience in Signal Integrity, Power Integrity, Platform Hardware Design, or Board Design. • Strong understanding of high-speed digital design and power delivery architectures. • Experience with high-speed PCB design and implementation. • Hands-on experience performing schematic review and board-level electrical analysis. • Knowledge of transmission line theory, channel modeling, termination techniques, and power distribution network

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/platform-signal-power-integrity-engineer-lead-at-intel-fec377

Source: https://jobsbylevel.com/jobs/platform-signal-power-integrity-engineer-lead-at-intel-fec377

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