# Power Delivery Integration and Power Rail Stress Engineer- SoC Power Thermal Performance Validation Engineer (Temporary position) at Intel

Intel is hiring a Power Delivery Integration and Power Rail Stress Engineer- SoC Power Thermal Performance Validation Engineer (Temporary position) in Guadalajara, Mexico. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/599b16e0-b1ff-4df7-a089-c91c10c81c2f?utm_medium=ai-agent).

AI Level 1, AI centrality 30 out of 100. Mexico, Guadalajara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 30 out of 100)
- Location: Mexico, Guadalajara
- Posted: November 6, 2026
- Apply: https://jobsbylevel.com/go/599b16e0-b1ff-4df7-a089-c91c10c81c2f?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=power-delivery-integration-and-power-rail-stress-engineer-soc-power-thermal-performance-validation-engineer-temporary-position-at-intel-dd9165

## Description

Job Details: Job Description: As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring Intel's products achieve optimal power, thermal, and performance benchmarks at the system-on-chip (SoC) level. In this position, you will develop and execute validation methodologies, optimize hardware/software solutions, and perform SoC-level debugging to address power, thermal, and performance challenges. Your contribution will directly impact Intel's ability to deliver competitive, high-performing products to market. This is a Temporary position (12 months) Key Responsibilities Develop and execute System-on-Chip (SoC)-level power delivery, Power Rails Stress (PRS), maximum current (ICCmax), current transient (di/dt), minimum/maximum voltage (Vmin/Vmax), Digital Linear Voltage Regulator (DLVR)/Fully Integrated Voltage Regulator (FIVR), and concurrency plans, including feasibility study and design/verification/simulation of the Power Distribution Network (PDN) and sign-off of IR-drop/Electromigration (IR/EM) metrics, across Intel products. Collaborate with architecture, design, firmware, software, Power Management architects, and layout teams to ensure power delivery meets competitive targets and specifications and to define and implement power gating solutions. Establish and execute methodologies for validating hardware/software optimizations and to converge the design on all Power Distribution Network (PDN) metrics, ensuring alignment with business Key Performance Indicators (KPIs). Perform System-on-Chip (SoC)-level debug to identify root causes and resolve functional and triage failures related to power delivery, on-die power grid/network, thermal, and performance. Configure and set up data loggers to collect and analyze power/thermal data, and work with the package integration team to ensure the complete IP system meets the design specification. Develop and maintain validation infrastructure (performance monitors, behavioral checkers, and testing environments) and work with the post-silicon debug team to triage, debug, and fix potential Power Distribution Network (PDN) issues. Produce comprehensive validation reports summarizing activities and results and communicate findings effectively with relevant teams. Drive continuous improvements to validation strategies, methodologies, and processes. The ideal candidate should show the following behavioral traits Strong analytical and problem-solving skills. Effective communication and documentation skills for cross-functional collaboration. Advanced teamwork to work across teams in multi-faceted groups (architecture, design, verification, firmware, software, and platform teams). Qualifications: Minimum qualifications , you must possess the below minimum qualifications to be initially considered for this position. Bachelor’s degree in Electronics, Electrical, Computer Engineering, or related field. 1+ years of experience in System-on-Chip (SoC) power and performance validation and/or digital logic and optimization. 1+ years of experience developing and / or optimization of power/performance Key Performance Indicators (KPIs) and/or circuit design trade-off for power, performance, and area. Intermediate to advanced English level. Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship). Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. A master's degree is preferred. Debugging experience for System-on-Chip (SoC)-level power, thermal, and performance failures. Power Delivery design, implementation, and validation of high-performance and low-power designs. Knowledge of hardware/software optimizations for power and performance. Low power implementation techniques. Experience with System-on-Chip (SoC)-level debug using Joint Test Action Group (JTAG) debuggers. Familiarity with validation tools

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/power-delivery-integration-and-power-rail-stress-engineer-soc-power-thermal-performance-validation-engineer-temporary-position-at-intel-dd9165

Source: https://jobsbylevel.com/jobs/power-delivery-integration-and-power-rail-stress-engineer-soc-power-thermal-performance-validation-engineer-temporary-position-at-intel-dd9165

## Cite this page

Level. https://jobsbylevel.com/jobs/power-delivery-integration-and-power-rail-stress-engineer-soc-power-thermal-performance-validation-engineer-temporary-position-at-intel-dd9165.

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