# Pre-Silicon SoC Validation - Technical Lead at Intel

Intel is hiring a Pre-Silicon SoC Validation - Technical Lead in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/50110d50-43be-4d2a-8a8b-4d78b16eeac5).

AI Level 1, AI centrality 31 out of 100. India, Bangalore.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 31 out of 100)
- Location: India, Bangalore
- Posted: October 8, 2026
- Apply: https://jobsbylevel.com/go/50110d50-43be-4d2a-8a8b-4d78b16eeac5

## Description

Job Details: Job Description: Role Summary: Seeking an experienced SoC Validation Engineer to define, drive, and execute validation strategies across the full silicon lifecycle, from architecture definition and pre-silicon planning through silicon power-on, post-silicon debug, stepping readiness, and PRQ quality convergence. The role requires deep expertise in complex SoC validation, security validation, coherency flows, firmware and hardware interaction, disaggregated architecture, and cross-functional technical leadership. The engineer will be responsible for ensuring early risk identification, high-quality milestone readiness, predictable silicon bring-up, rapid sighting debug, and continuous feedback from post-silicon learnings into earlier validation phases. Key Responsibilities: Define and drive end-to-end SoC validation strategy across the full lifecycle, including architecture definition, pre-silicon validation planning, RTL milestone readiness, silicon power-on preparation, post-silicon debug, stepping readiness, and PRQ quality convergence. Develop comprehensive validation plans, execution strategies, coverage goals, debug plans, and sign-off criteria aligned to program milestones and product quality targets. Drive validation of critical SoC flows across security, coherency, memory, fabric, IO, and cross-die interactions in disaggregated architectures. Validate complex hardware, firmware, and software interactions with specific focus on security handshakes, coherency protocols, cache and fabric ordering, access control, isolation, attestation, fuse/security policy behavior, and multi-die/domain interactions. Review architecture and microarchitecture specifications to identify validation gaps in security, coherency, shared-resource behavior, cross-die communication, firmware sequencing, and lifecycle readiness from pre-silicon through post-silicon execution. Drive debug of complex pre-silicon and post-silicon failures, identify root cause across RTL, firmware, microcode, platform software, validation content, security policy, coherency behavior, and system-level configuration. Partner with architecture, design, verification, firmware, post-silicon, security, coherency, platform, manufacturing, and program teams to ensure high-quality validation readiness, silicon bring-up efficiency, and timely closure of issues across product milestones. Use post-silicon sightings, customer issues, stepping feedback, defect trends, security observations, and coherency escapes to strengthen earlier validation strategies, improve coverage, and prevent repeated escapes across programs. Define validation quality metrics, execution dashboards, risk indicators, milestone readiness reports, and sign-off recommendations for leadership reviews. Drive innovation in validation efficiency, including automation, test grading, coverage-driven execution, AI/ML-assisted bug hunting, regression optimization, and shift-left methodologies. Mentor senior and mid-level engineers, build technical depth in the team, and contribute to reusable validation methodologies, collateral, and best practices across programs. Qualifications: Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, Embedded Systems, Computer Science, or a related discipline. 12-20 years of relevant industry experience in pre-silicon validation, SoC validation, design verification, silicon validation, firmware validation, or hardware/software co-validation. Strong understanding of SoC architecture, microarchitecture, CPU/core integration, fabrics, memory subsystem, security, coherency, cache hierarchy, firmware-driven security flows, and disaggregated/multi-die architectures. Hands-on experience defining and executing validation strategies across the product lifecycle, including architecture review, pre-silicon planning, RTL milestone readiness, silicon power-on preparation, post-silicon sighting debug, stepping feedback, and PRQ

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/pre-silicon-soc-validation-technical-lead-at-intel-384c25

Source: https://jobsbylevel.com/jobs/pre-silicon-soc-validation-technical-lead-at-intel-384c25

## Cite this page

Level. https://jobsbylevel.com/jobs/pre-silicon-soc-validation-technical-lead-at-intel-384c25.

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