# Principal Design Verifiction Engineer at SambaNova Systems

SambaNova Systems is hiring a Principal Design Verifiction Engineer in San Jose, United States. It pays $180k-$225k a year and Level rates it Little AI ●○○○; you can [apply on SambaNova Systems](https://jobsbylevel.com/go/2c4e4438-ef53-44fb-9509-e312ca7ff64d?utm_medium=ai-agent).

AI Level 1, AI centrality 11 out of 100. San Jose, California, United States.

## Details

- Company: [SambaNova Systems](https://jobsbylevel.com/companies/sambanova-systems)
- AI level: AI Level 1 (score 11 out of 100)
- Location: San Jose, California, United States
- Salary: $180k-$225k
- Posted: November 13, 2026
- Apply: https://jobsbylevel.com/go/2c4e4438-ef53-44fb-9509-e312ca7ff64d?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=principal-design-verifiction-engineer-at-sambanova-systems-e9107f

## Description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. Job Overview SambaNova Systems is looking for a Principal Design Verification Engineer to own verification for a major subsystem of our next-generation RDU — the reconfigurable dataflow silicon behind our machine learning and AI systems. This is a senior individual-contributor role with real ownership. You will own the test plan, testbench architecture, coverage model, formal verification and sign-off criteria for your area, and you will be the person the team looks to when the hardest failures need root-causing. You will also shape methodology beyond your own subsystem: the infrastructure, reuse patterns, and verification practices the rest of the team builds on. You will work alongside principal engineers who have built and evolved this verification environment across several generations of silicon, and with design, architecture, compiler, and runtime teams to make sure the chip is verified against real ML workloads. Roles and Responsibilities Define and own the verification execution plan end to end for a major subsystem of the RDU — test plan, testbench architecture, coverage model, formal verification, and sign-off criteria Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures Verify functional and performance behavior Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out Own regression health and failure triage for your area — drive root cause, not just reproduction Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level Advance DV methodology beyond your own area — reusable infrastructure, verification IP integration, and AI-assisted verification workflows Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab Set the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice Minimum Qualifications BS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++ Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause Demonstrated technical leadership without formal authority — setting direction in reviews, arbitrating testbench decisions, and mentoring engineers Working knowledge of modern computer architecture and of machine learning accelerators or SoCs Preferred Qualifications MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification Depth in high-speed I/O verification — protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR Performance verification methodology — building performance benches and analyzing results, not only functional correctness Formal verification and assertion-based methods Experience evaluating, integrating, and validating third-party verification IP Gate-level simulation and debug

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/principal-design-verifiction-engineer-at-sambanova-systems-e9107f

Source: https://jobsbylevel.com/jobs/principal-design-verifiction-engineer-at-sambanova-systems-e9107f

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