# Product Engineer, Silicon Validation at Etched

Etched is hiring a Product Engineer, Silicon Validation in San Jose, United States. Level rates it Works on AI ●●●○; you can [apply on Etched](https://jobsbylevel.com/go/90522965-f511-4df0-aee6-c3e0d10afa88?utm_medium=ai-agent).

AI Level 3, AI centrality 60 out of 100. San Jose.

## Details

- Company: [Etched](https://jobsbylevel.com/companies/etched)
- AI level: AI Level 3 (score 60 out of 100)
- Location: San Jose
- Posted: May 6, 2026
- Apply: https://jobsbylevel.com/go/90522965-f511-4df0-aee6-c3e0d10afa88?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=product-engineer-silicon-validation-at-etched-8d37ac

## Prepare for this job

The job page lists 5 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/product-engineer-silicon-validation-at-etched-8d37ac

## Description

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking an experienced Product Engineer to lead silicon validation, test program development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions. Key Responsibilities Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting Lead test cost optimization efforts while maintaining quality standards Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods Establish and track key quality metrics including DPPM and test escapes Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs Manage relationships with test vendors, OSAT partners, and foundry partners You may be a good fit if you have (Must-have qualifications) Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors Proven track record in yield optimization and DPPM reduction with quantifiable results Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation High-volume manufacturing test experience with demonstrated production scale results Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques Strong candidates may also have experience with (Nice-to-have qualifications) Experience developing and optimizing ATE test programs for wafer sort and final test on Advantest V93K platforms Experience managing wafer sort and final test across multiple advanced process nodes GPU, HPC, or AI accelerator chip testing background with production scale results HBM or high-speed memory interface testing and characterization experience Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites Driving significant cost reduction initiatives Multi-site parallel testing strategies and test time optimization for large-format dies Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation Cross-functional leadership in silicon bring-up and manufacturing ramp Benefits Medical, dental, and vision packages with generous premium coverage

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/product-engineer-silicon-validation-at-etched-8d37ac

Source: https://jobsbylevel.com/jobs/product-engineer-silicon-validation-at-etched-8d37ac

## Cite this page

Level. https://jobsbylevel.com/jobs/product-engineer-silicon-validation-at-etched-8d37ac.

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