# Senior Analog and Mixed Signal Design Engineer at Intel

Intel is hiring a Senior Analog and Mixed Signal Design Engineer. It pays $142k-$269k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/a7a21150-1b07-4219-945c-f1afe4ec4998?utm_medium=ai-agent).

AI Level 1, AI centrality 30 out of 100. US, Oregon, Hillsboro.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 30 out of 100)
- Location: US, Oregon, Hillsboro
- Salary: $142k-$269k
- Posted: October 26, 2026
- Apply: https://jobsbylevel.com/go/a7a21150-1b07-4219-945c-f1afe4ec4998?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-analog-and-mixed-signal-design-engineer-at-intel-ef6708

## Description

Job Details: Job Description: The Group Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver. The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM. The Role We are seeking a senior technical expert in high-speed SerDes circuit design and SerDes system architecture. You will own SerDes link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks. You will also translate link requirements into device, interconnect, and design-rule requirements that shape future Intel process nodes. This is a senior individual-contributor role with technical leadership across design, layout, and measurement engineers. Responsibilities Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers. Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits. Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution. Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps. Translate SerDes requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams. Provide technical leadership: mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design, -OR- Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline SerDes circuit design. Experience in Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher. Experience in at least one of the following: SerDes link architecture: channel and link-budget analysis or equalization trade-off studies used to set block-level specifications. Lab validation of high-speed links: BER, eye, or jitter measurement and correlation to simulation. Behavioral or statistical link modeling in MATLAB or Python. Preferred Qualifications Experience with Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS; multiple tape-outs with block ownership.

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Source: https://jobsbylevel.com/jobs/senior-analog-and-mixed-signal-design-engineer-at-intel-ef6708

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