# Senior ASIC DFT DV Engineer (Hybrid) at Cisco

Cisco is hiring a Senior ASIC DFT DV Engineer (Hybrid) in San Jose, United States. It pays $168k-$245k a year and Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/f274c508-d4fe-47ae-84cc-8d80d7787a6d?utm_medium=ai-agent).

AI Level 1, AI centrality 33 out of 100. San Jose, California, US.

## Details

- Company: [Cisco](https://jobsbylevel.com/companies/cisco)
- AI level: AI Level 1 (score 33 out of 100)
- Location: San Jose, California, US
- Salary: $168k-$245k
- Posted: October 13, 2026
- Apply: https://jobsbylevel.com/go/f274c508-d4fe-47ae-84cc-8d80d7787a6d?utm_medium=ai-agent

## Description

The application window is expected to close on: 11/12/2026 This is a hybrid role with three days per week at Cisco’s San Jose location Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact ​ Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design Own the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing. Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon. Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum Qualifications ​ Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience. Prior experience in test planning based on complex design specification Experience debugging using DVE/Verdi. Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.​ Experience with TCL, Python or Perl. Preferred qualifications​ Experience in Verilog/SV Experience addressing memory failure correlation in production Experience in silicon testing and Automatic Test Equipment (ATE) Experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent).​ Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-asic-dft-dv-engineer-hybrid-at-cisco-c645dc

Source: https://jobsbylevel.com/jobs/senior-asic-dft-dv-engineer-hybrid-at-cisco-c645dc

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-asic-dft-dv-engineer-hybrid-at-cisco-c645dc.

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