# Senior ASIC Physical Design Engineer at Hewlett Packard Enterprise

Hewlett Packard Enterprise is hiring a Senior ASIC Physical Design Engineer. Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/a4700e05-2db4-4c9c-95ad-325a0720a465).

AI Level 1, AI centrality 31 out of 100. Ft. Collins, Colorado, United States of America.

## Details

- Company: [Hewlett Packard Enterprise](https://jobsbylevel.com/companies/hewlett-packard-enterprise)
- AI level: AI Level 1 (score 31 out of 100)
- Location: Ft. Collins, Colorado, United States of America
- Posted: October 8, 2026
- Apply: https://jobsbylevel.com/go/a4700e05-2db4-4c9c-95ad-325a0720a465

## Description

Senior ASIC Physical Design Engineer This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: About the Role HPE is seeking an experienced ASIC Physical Design Engineer to support the development of complex, high-performance integrated circuits. In this role, you will contribute to design quality, synthesis, formal verification, partitioning, floorplanning, timing analysis, timing closure, and signoff activities. You will collaborate closely with ASIC design, physical implementation, DFT, signal integrity, architecture, and other cross-functional teams to develop physically aware designs and scalable implementation methodologies. This role offers the opportunity to work with advanced process technologies and contribute to complex ASIC products and platforms. What You'll Do Perform static timing analysis for hierarchical designs at both partition and full-chip levels. Create, validate, and maintain timing constraints and timing budgets for design and process requirements. Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing. Analyze timing reports, identify critical paths, and implement fixes to achieve performance, power, and area objectives. Perform synthesis, netlist quality checks, and formal verification. Support chip partitioning, floorplanning, and physical design implementation. Create and manage functional engineering change orders (ECOs). Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff. Partner with cross-functional engineering teams to promote physical-design-aware architecture and implementation. Review design and project activities for compliance with ASIC technology, methodology, and development standards. Provide technical guidance and mentoring to less-experienced engineers and contribute to continuous improvement across the design organization. What You Need Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field. Typically 6–10 years of experience in ASIC, VLSI, or semiconductor design implementation, with relevant experience in physical design and timing closure. Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design. Experience with one or more of the following: Static timing analysis and timing signoff Timing constraints and validation Synthesis and netlist quality analysis Formal verification Floorplanning and chip partitioning ECO implementation Experience with industry-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, or Formality, and/or Cadence RTL Compiler, Genus, or LEC. Proficiency in scripting and flow automation using Perl, Python, Tcl, or similar languages. Strong analytical, problem-solving, and debugging skills. Effective written and verbal communication skills in English. Ability to work independently and collaboratively across multiple engineering disciplines. Preferred Qualifications Experience with hierarchical timing analysis and full-chip timing closure. Experience with clock, I/O, test,

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-asic-physical-design-engineer-at-hewlett-packard-enterprise-3a38c3

Source: https://jobsbylevel.com/jobs/senior-asic-physical-design-engineer-at-hewlett-packard-enterprise-3a38c3

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-asic-physical-design-engineer-at-hewlett-packard-enterprise-3a38c3.

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