# Senior ASIC Verification Engineer at Hewlett Packard Enterprise

Hewlett Packard Enterprise is hiring a Senior ASIC Verification Engineer in Sunnyvale, United States. Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/0b3b0f17-cb0a-49ae-872e-854f6b5a78fc).

AI Level 1, AI centrality 32 out of 100. Sunnyvale, California, United States of America.

## Details

- Company: [Hewlett Packard Enterprise](https://jobsbylevel.com/companies/hewlett-packard-enterprise)
- AI level: AI Level 1 (score 32 out of 100)
- Location: Sunnyvale, California, United States of America
- Posted: October 8, 2026
- Apply: https://jobsbylevel.com/go/0b3b0f17-cb0a-49ae-872e-854f6b5a78fc

## Description

Senior ASIC Verification Engineer This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Management Level Definition: Contributions impact technical components of HPE products, solutions, or services regularly and sustainable. Applies advanced subject matter knowledge to solve complex business issues and is regarded as a subject matter expert. Provides expertise and partnership to functional and technical project teams and may participate in cross-functional initiatives. Exercises significant independent judgment to determine best method for achieving objectives. May provide team leadership and mentoring to others. Responsibilities: Provide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing. Reviews and evaluates designs and project activities for compliance with VLSI technology and development guidelines and standards; provides tangible feedback to improve product quality. Provides VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities. Provides leadership of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products. Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence. Participates in and provides input on process for selection of future technical leaders. Drives VLSI innovation and integration of new technologies into projects and activities in the design organization. You will start with a functional specification of a module and produce a detailed test plan to verify the module. You will write functional models for the module using System Verilog/C/C++ for architectural validation. You will build the module level test bench using System Verilog/UVM You will write tests according to the test plan to thoroughly verify the module. You will b e responsible for making sure your module is fully functional. You will work closely with logic designers to resolve bugs, with SW engineers to assist in driver code development. You will use state - of - the - art tools for doing formal verification, code coverage analysis, gate sims, and more. You will also get a chance to be part of full chip/sub-system and

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-asic-verification-engineer-at-hewlett-packard-enterprise-b50add

Source: https://jobsbylevel.com/jobs/senior-asic-verification-engineer-at-hewlett-packard-enterprise-b50add

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-asic-verification-engineer-at-hewlett-packard-enterprise-b50add.

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