# Senior Design Verification Engineer at Intel

Intel is hiring a Senior Design Verification Engineer in Santa Clara, United States. It pays $191k-$269k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/524daaed-7ca3-4d0b-9ba7-4a0013b042cc?utm_medium=ai-agent).

AI Level 1, AI centrality 25 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 25 out of 100)
- Location: US, California, Santa Clara
- Salary: $191k-$269k
- Posted: November 11, 2026
- Apply: https://jobsbylevel.com/go/524daaed-7ca3-4d0b-9ba7-4a0013b042cc?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-design-verification-engineer-at-intel-9aa1fa

## Description

Job Details: Job Description: About the Team Intel is building something new. The Unified Intel Chassis (UIC) team is a new IP development team focused on chassis and interconnect technology and a configurable generator for SoCs and chiplets. As a Senior Design Verification Engineer, you will verify coherent, non-coherent, and I/O-coherent systems — including interactions among interconnects, caches, memory subsystems, and chassis functions such as clocking, power management, reset, debug, and trace. This is a hands-on technical role spanning the full verification lifecycle: from clarifying requirements and building models and checkers through debugging and verification signoff. You will work closely with engineers across architecture, design, verification, and tooling to turn specifications into working, tested hardware. Simulation, formal verification, and AI-assisted development are part of how we work. Key Responsibilities Own verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive assigned features from initial bring-up through signoff Build reusable environments, reference models, and checkers for data integrity, ordering, address translation, access permissions, interrupt routing and delivery, and forward progress under concurrent traffic and backpressure Combine simulation, formal properties, and targeted experiments to find bugs; review assumptions, checker completeness, coverage gaps, and proof results rather than relying on passing regressions alone Collaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions Work with architecture, design, and tooling engineers to clarify specifications, evaluate tradeoffs, and contribute reviewed changes to models, RTL, and verification infrastructure Develop configuration-driven regressions and AI-assisted workflows for coding, property development, and debug; validate generated work with independent checks and reproducible tests across supported configurations Mentor engineers through code and testplan reviews, communicate remaining risks, and establish clear evidence for verification closure What We're Looking For You should demonstrate the following professional traits to be successful: Demonstrated ownership of complex verification work through closure, including cross-block root-cause analysis and clear technical communication across engineering disciplines A collaborative approach to working across architecture, design, and verification teams to define requirements, resolve ambiguity, and drive toward shared goals A rigorous, evidence-driven mindset — one that questions assumptions, validates generated work independently, and communicates risk clearly rather than relying on surface-level indicators of completeness Qualifications: Minimum Qualifications BS/MS in Electrical Engineering, Computer Science, or related field with 10+ years of relevant experience in design verification; background in IP DV with significant experience in subsystem and SoC-level verification The experience must include: Hands-on experience verifying high-performance interconnects and memory subsystems, with an understanding of coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, I/O Memory management units (IOMMUs), and interrupt controllers; experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures SystemVerilog/UVM and assertion-based verification skills, with practical experience applying formal verification alongside simulation and understanding the limits of each method Programming and debugging skills in SystemVerilog and Python or C/C++; ability to read RTL, build independent reference models and checkers, and develop maintainable test automation

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-design-verification-engineer-at-intel-9aa1fa

Source: https://jobsbylevel.com/jobs/senior-design-verification-engineer-at-intel-9aa1fa

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