# Senior DFT Design Engineer at Intel

Intel is hiring a Senior DFT Design Engineer. It pays $142k-$173k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/c01a277e-ed44-4aad-bcf4-c9098a1a79c9?utm_medium=ai-agent).

AI Level 1, AI centrality 32 out of 100. US, California, Folsom.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 32 out of 100)
- Location: US, California, Folsom
- Salary: $142k-$173k
- Posted: November 3, 2026
- Apply: https://jobsbylevel.com/go/c01a277e-ed44-4aad-bcf4-c9098a1a79c9?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-dft-design-engineer-at-intel-95e28e

## Description

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role and Impact We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of ATPG content Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. Business Group The Data Center Group (DCG) develops advanced technologies that power data-intensive workloads across industries. As part of DCG, the GPU Hardware IP (GHI) team designs and validates next-generation graphics engines. The group's mission focuses on innovation in visual computing and delivering high-performance solutions that propel Intel's leadership in graphics. Joining this team means shaping the future of GPU development and contributing to impactful technologies. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 1+ years of industry experience. Your experience should be in following - Scan, ATPG or other DFT features. - SoC or IP DFT design, integration or verification. - EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS and/or other simulation or debug tools. Preferred Qualifications: Silicon enabling debug or test pattern development experience. Design automation skills and proficiency in programming or scripting languages. Structural design flows, including timing, routing, placement or clocking analysis. High volume manufacturing requirements and test flows. 3D, media and display graphics pipelines. SoC architecture. Job Type: Experienced Hire Shift: Shift 1

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-dft-design-engineer-at-intel-95e28e

Source: https://jobsbylevel.com/jobs/senior-dft-design-engineer-at-intel-95e28e

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