# Senior EDA Tools Hardware Engineer at Intel

Intel is hiring a Senior EDA Tools Hardware Engineer in Santa Clara, United States. It pays $142k-$269k a year and Level rates it Little AI ●○○○; you can [apply on Level](https://jobsbylevel.com/go/c13acaf8-a3a4-4967-814d-90e40c53090b).

AI Level 1, AI centrality 0 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: US, California, Santa Clara
- Salary: $142k-$269k
- Posted: October 8, 2026
- Apply: https://jobsbylevel.com/go/c13acaf8-a3a4-4967-814d-90e40c53090b

## Description

Job Details: Job Description: The Role and Impact Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies. This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows. The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate. Key Responsibilities Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance. Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows. Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes. Define and enable methodologies for hardware development related to EDA tools and technology node advancements. Support and enhance platforms, databases, scripts, and tools used for design automation. Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Degree in one of the following options: Option 1: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience. Option 2: Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience. Option 3: Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience. 3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or PrimeLib). Experience with Liberty timing models. Preferred Qualifications Experience in any of the following: SPICE simulation CMOS circuits Memory architecture fundamentals STA fundamentals Advanced-node custom IP or memory characterization flows Scripting and automation skills in Linux environments Take the next step in your career by joining Intel and becoming a part of our mission to shape the future of technology. Apply today to make an impact with your expertise. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-eda-tools-hardware-engineer-at-intel-4da433

Source: https://jobsbylevel.com/jobs/senior-eda-tools-hardware-engineer-at-intel-4da433

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-eda-tools-hardware-engineer-at-intel-4da433.

Get job alerts: https://jobsbylevel.com/newsletter