# Senior Mixed Signal Post Silicon Validation Engineer IOs at Intel

Intel is hiring a Senior Mixed Signal Post Silicon Validation Engineer IOs. It pays $142k-$200k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/c9f6a482-d4b8-4d6f-a2e6-77af0295fac3?utm_medium=ai-agent).

AI Level 1, AI centrality 34 out of 100. US, California, Folsom.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 34 out of 100)
- Location: US, California, Folsom
- Salary: $142k-$200k
- Posted: November 9, 2026
- Apply: https://jobsbylevel.com/go/c9f6a482-d4b8-4d6f-a2e6-77af0295fac3?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-mixed-signal-post-silicon-validation-engineer-ios-at-intel-973292

## Description

Job Details: Job Description: About the Team The Hard IP Development Group (HIPD) within Intel's Central Engineering Organization is responsible for developing leadership IPs that are power-winning products for Server, Client, and Networking SOCs, as well as Intel Foundry Customers. HIPD develops a broad portfolio of Serial and Parallel IO PHYs including PCIe, USB, TypeC, UCIe Die-to-Die, DDR/LPDDR, and Ethernet PHYs. The Electrical Validation and Debug group within HIPD is a dynamic and versatile team of engineers who directly engage with both IP design teams and SOC customers in IP validation and debug for test chips and products. These engineers embody our SOC customer obsession by validating mixed signal IPs and quickly resolving hurdles through hands-on debug. This position is exciting and challenging, offering the opportunity to exercise your mixed signal design, architecture, and post-silicon debug expertise across all HIPD IPs, Client, and Server SOC teams. Position Overview This role focuses on mixed signal high-speed PHY post-silicon validation and debug, spanning IP enabling, customer sighting resolution, and cross-functional collaboration with SOC teams. Key Responsibilities • Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks • Perform IO protocol debug across one or more of the following: PCIe, UCIe, DDR, or Ethernet, from both PHY recipe and firmware perspectives • Conduct SOC board design reviews, provide recommendations, and support post-silicon debug activities • Represent the IP team during SOC Power-Ons for test chips and products, providing hands-on IP enabling support through proper recipes and firmware versions for PCIe, UCIe, and USB PHYs • Identify clocking and PHY-related silicon issues, investigate, debug, and disposition customer bugs and sightings in a timely manner • Reproduce customer issues and drive root cause analysis through failure analysis and structured debug methodologies You Should Demonstrate the Following Professional Traits to Be Successful Customer obsession with a strong sense of urgency in resolving technical issues Versatility and adaptability when engaging across multiple teams, IPs, and debug scenarios Collaborative mindset with the ability to work effectively with both IP design teams and SOC customers Qualifications: Minimum Qualifications • BS with 6+ years, MS with 4+ years, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field • Relevant years of experience (as outlined above) in electrical or bench post-silicon validation with one or more high-speed PHYs such as PCIe, USB, UCIe, DDR, Ethernet, or equivalent interface experience The experience must also include: • Experience with lab hardware and software including Oscilloscopes, Logic Analyzers, Protocol Analyzers, and BERTs • Knowledge of one or more industry-standard IO specifications such as PCIe, USB, or Die-to-Die UCIe Preferred Qualifications • Experience with mixed signal IP characterization including PLLs, TX and RX jitter characterization • Experience leading IP debug efforts as situations arise, in addition to hands-on debug execution • Signal integrity and power delivery knowledge • Pre-silicon design or simulation experience in logic, circuits, firmware, MRC, or mixed signal validation Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-mixed-signal-post-silicon-validation-engineer-ios-at-intel-973292

Source: https://jobsbylevel.com/jobs/senior-mixed-signal-post-silicon-validation-engineer-ios-at-intel-973292

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-mixed-signal-post-silicon-validation-engineer-ios-at-intel-973292.

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