# Senior PDK Physical Verification Engineer at Intel

Intel is hiring a Senior PDK Physical Verification Engineer. It pays $150k-$285k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/e00b318d-cbec-4875-bee0-93acb24adf6f?utm_medium=ai-agent).

AI Level 1, AI centrality 33 out of 100. US, Oregon, Hillsboro.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 33 out of 100)
- Location: US, Oregon, Hillsboro
- Salary: $150k-$285k
- Posted: October 28, 2026
- Apply: https://jobsbylevel.com/go/e00b318d-cbec-4875-bee0-93acb24adf6f?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-pdk-physical-verification-engineer-at-intel-e0bd69

## Description

Job Details: Job Description: Shape the Future of Advanced Semiconductor Technology at Intel Join Intel's Design Technology Platform (DTP) organization and become part of a world-class team enabling the next generation of semiconductor innovation. In this highly visible role, you will develop and deploy advanced density fill methodologies and Process Design Kit (PDK) solutions that directly impact Intel's most advanced technology nodes and product designs. Working at the intersection of process technology, physical verification, and design automation, you will collaborate with leading engineers across Intel and the EDA ecosystem to solve complex manufacturability challenges, improve design productivity, and enable breakthrough technologies. Your contributions will influence how future products are designed and manufactured, helping Intel maintain technology leadership in an increasingly competitive industry. What You'll Do Lead the development, implementation, and validation of density fill solutions within advanced Process Design Kits (PDKs). Develop algorithmic solutions using industry-leading physical verification platforms, including Calibre, Synopsys ICV, and Cadence Pegasus, to ensure density compliance and manufacturability across advanced process technologies. Collaborate with process integration teams, design rule owners, product design engineers, and customers to define requirements and deliver state-of-the-art solutions. Drive automation initiatives that improve engineering efficiency, solution scalability, and deployment across multiple design environments. Design and develop robust validation frameworks, test suites, and qualification methodologies to ensure high-quality tool and rule deck releases. Advance innovative physical verification methodologies to address emerging challenges associated with technology scaling. Partner closely with external EDA vendors to influence and deploy next-generation tool capabilities and methodologies. Develop technical documentation, training materials, and best practices that enable successful adoption across Intel's design community. Serve as a technical expert and contribute to strategic initiatives that shape Intel's design enablement roadmap. Ideal Candidate Background We are particularly interested in candidates who have developed physical verification methodologies, density-fill solutions, or PDK technologies within: Semiconductor Foundries. Integrated Device Manufacturers (IDMs). Advanced Packaging and OSAT Organizations. EDA Software Companies. Design Enablement or CAD Teams supporting advanced-node development. Core Competencies Excellent communication and technical presentation skills, with the ability to translate complex technical concepts into actionable solutions. Strong problem-solving, debugging, and analytical skills. Strong understanding of technology scaling challenges and their impact on physical verification and design rule development. Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience; OR - Master's degree with 5+ years of experience. OR - PhD with 2+ years of experience. 4+ years of hands-on experience with at least one industry-standard physical verification platform such as Calibre, ICV, or Pegasus, including methodology development, rule deck debugging, validation, or production deployment. 3+ years of experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-pdk-physical-verification-engineer-at-intel-e0bd69

Source: https://jobsbylevel.com/jobs/senior-pdk-physical-verification-engineer-at-intel-e0bd69

## Cite this page

Level. https://jobsbylevel.com/jobs/senior-pdk-physical-verification-engineer-at-intel-e0bd69.

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