# Senior Principal Engineer, Device Design at Intel

Intel is hiring a Senior Principal Engineer, Device Design. It pays $265k-$375k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/844725e8-737d-4115-ad74-3344b0bdbb58?utm_medium=ai-agent).

AI Level 1, AI centrality 34 out of 100. US, Oregon, Hillsboro.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 34 out of 100)
- Location: US, Oregon, Hillsboro
- Salary: $265k-$375k
- Posted: November 6, 2026
- Apply: https://jobsbylevel.com/go/844725e8-737d-4115-ad74-3344b0bdbb58?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=senior-principal-engineer-device-design-at-intel-cbaefe

## Description

Job Details: Job Description: About the Group Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading global foundry service provider, offering world-class manufacturing capabilities to external customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation-focusing on technology customization, yield improvement, performance optimization, and exceptional customer delivery. About the Role We are seeking a highly accomplished Senior Principal Device Design Engineer with broad semiconductor industry expertise to drive the high-level architecture, definition, and optimization of next-generation and high-volume manufacturing (HVM) semiconductor technologies. In this strategic technical leadership role, you will apply a deep mastery of semiconductor device physics to define technical roadmaps and ensure world-class performance across a diverse range of applications-including advanced logic, SRAM, low-power mobile, analog, and mixed-signal designs. Serving as a primary technical bridge between Process Integration, Yield, and Module Engineering, and collaborative product partners, you will establish the technical direction, target validations, and silicon-to-simulation accuracy across Intel's diverse technology portfolio. Key Responsibilities: Technical Strategy and Architecture Leadership: Lead cross-functional, multi-disciplinary teams in defining base and derivative semiconductor architectures-including advanced transistors, interconnects, and design rules-tailored for high-performance logic, low-power, memory, analog, and mixed-signal applications. Technical Partner and Customer Engagement: Partner directly with external customers, product design teams, and internal engineering groups to understand complex product requirements, resolve circuit-level performance/reliability/leakage trade-offs, and translate product needs into tailored silicon solutions. Technology Customization and Optimization: Drive the development and implementation of customized semiconductor features across logic and memory technologies, ensuring seamless integration with existing manufacturing processes and platforms to support specialized applications. Silicon-to-Simulation Readiness: Set and govern device and interconnect performance targets, evaluating silicon-to-simulation health, model readiness, and design feasibility for large-volume manufacturing. Cross-Functional Integration: Serve as the authoritative technical interface bridging Process Integration, Process Module, Device Physics, Yield Engineering, and Product Design to coordinate complex technology handoffs and resolve system-level constraints. Design Rule and Waiver Governance: Direct the validation and strategic waiver management processes for advanced design rules, balancing strict manufacturing compliance and yield with product design flexibility. Advanced Data Analytics: Guide the evaluation of electrical test (E-test) and yield data using advanced statistical methods and data analysis techniques to translate experimental silicon data into actionable process and design intelligence. Mentorship and Industry Thought Leadership: Provide senior technical mentorship to engineers and researchers across the organization, stay ahead of emerging semiconductor industry trends, and foster a culture of technical excellence and customer-centric innovation. Required Skills and Experience: Progressive experience in the semiconductor industry with a strong focus on CMOS device physics, device design, and semiconductor technology development. Leadership and Technology Integration: Demonstrated technical leadership within the semiconductor industry, specifically leading cross-functional teams to define, develop, and deliver advanced semiconductor technologies (covering logic, memory, or integrated architectures) and design rules into High-Volume Manufacturing (HVM). Design Rule Governance: Deep proficiency in

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/senior-principal-engineer-device-design-at-intel-cbaefe

Source: https://jobsbylevel.com/jobs/senior-principal-engineer-device-design-at-intel-cbaefe

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