# Silicon Packaging Design Engineer at Intel

Intel is hiring a Silicon Packaging Design Engineer in Phoenix, United States. It pays $91k-$173k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/dc1a933d-6c22-4391-b6b7-dda61cb5fbda?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. US, Arizona, Phoenix.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: US, Arizona, Phoenix
- Salary: $91k-$173k
- Posted: November 12, 2026
- Apply: https://jobsbylevel.com/go/dc1a933d-6c22-4391-b6b7-dda61cb5fbda?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=silicon-packaging-design-engineer-at-intel-7e9d4f

## Prepare for this job

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## Description

Job Details: Job Description: The Opportunity Join Intel's advanced packaging team and help shape the future of high-performance computing. As a Silicon Packaging Design Engineer, you will be responsible for the design and development of next-generation package substrates that enable industry-leading semiconductor products. Working closely with silicon, signal integrity, power delivery, manufacturing, and hardware teams, you will drive substrate solutions from initial concept through tapeout, balancing electrical performance, manufacturability, cost, and schedule requirements. This role offers the opportunity to influence cutting-edge packaging technologies that support Intel's most advanced products and platforms. Key Responsibilities Design and develop microelectronic package substrates from architecture definition through final tapeout. Create and optimize physical package layouts, including high-density routing solutions that meet electrical, mechanical, thermal, and manufacturability requirements. Perform substrate feasibility, fit, and routing studies to evaluate design tradeoffs involving performance, complexity, cost, and schedule. Define, implement, and maintain substrate design rules while conducting design reviews with internal and external stakeholders. Analyze and resolve design rule check (DRC) violations and other layout-related issues to ensure design quality and robustness. Collaborate with silicon, package, board, signal integrity, power integrity, and manufacturing teams to optimize pinouts and system-level connectivity. Drive continuous improvements in package design methodologies, automation, and best practices. Generate and maintain design documentation, technical reports, and engineering deliverables within product lifecycle management systems. Support package bring-up, qualification, and debug activities as needed. Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications US Citizenship required. Ability to obtain US Government TS/SCI Security Clearance. Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline and 6+ months of experience. Experience or academic exposure with microelectronic package or PCB physical layout design and manufacturing process. Experience with with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks. Experience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion. Preferred Qualifications Post Graduate degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline. Active US Government TS/SCI Security Clearance. Experience with semiconductor package substrate design, package I/O planning, and high-density routing technologies. Knowledge of advanced packaging technologies such as flip-chip, 2.5D, 3D packaging, chiplets, embedded bridge, or high-bandwidth interconnect solutions. Familiarity with package electrical analysis and simulation tools including HyperLynx, PowerDC, Ansys HFSS, and Ansys Q3D. Experience using package automation and productivity tools such as Package Layout Automation (PLA) and FIELD. Programming or scripting experience using Python, VB, C/C++, or similar languages to drive design automation and workflow improvements. Proven ability to troubleshoot complex design challenges and develop innovative engineering solutions in a fast-paced environment. Why Intel At Intel, you'll work alongside world-class engineers developing technologies that power everything

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