# Silicon Product Engineer – Manufacturing at NVIDIA

NVIDIA is hiring a Silicon Product Engineer – Manufacturing in Santa Clara, United States. It pays $116k-$190k a year and Level rates it Little AI ●○○○; you can [apply on NVIDIA](https://jobsbylevel.com/go/a32fa214-9ce4-4045-b011-49997101ace8?utm_medium=ai-agent).

AI Level 1, AI centrality 21 out of 100. US, CA, Santa Clara.

## Details

- Company: [NVIDIA](https://jobsbylevel.com/companies/nvidia)
- AI level: AI Level 1 (score 21 out of 100)
- Location: US, CA, Santa Clara
- Salary: $116k-$190k
- Posted: October 28, 2026
- Apply: https://jobsbylevel.com/go/a32fa214-9ce4-4045-b011-49997101ace8?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=silicon-product-engineer-manufacturing-at-nvidia-aa9cb3

## Description

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. Our team gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Silicon Product Engineer – Manufacturing to join our Testability, Manufacturability, Reliability & Quality (TMRQ) team. In this role, you will help validate and implement SLT/BLT Production diagnostics and test specs for silicon features in a high-volume manufacturing environment, verify POR specifications, and support post-silicon validation for some of the industry’s most complex semiconductor chips. You should have experience defining and validating SLT/BLT production coverage specifications on silicon and translating product requirements into effective test coverage that delivers quality, yield, and efficiency at scale. Hands-on lab experience with system-level post-silicon bring-up and silicon debugging is required. This role sits at the intersection of multi-functional HW/SW teams and Production Operations to make manufacturing an outstanding part of the overall Silicon co-design cycle, production release, and HVM testing! The exceptional hire continuously improves high-volume manufacturing workflows and products across functions and deliberately uses AI to drive impact while handling risk! What you will be doing: Responsible for developing and implementing robust closed-loop analysis for VF characteristics and POR expectations vs. production screens to improve overall quality of MFG screening diags. Support VF/VMIN/VMAX/PVT spec validation and productization activities across Manufacturing teams and product segments. Partner multi-functionally with HW engineering teams such as Silicon PVT design and characterization teams, IO design and validation teams, system feature owners, SLT and BLT Production Operations, etc., to determine test coverage and constraints to resolve appropriate SLT/BLT test conditions, test content, and flows for high-volume manufacturing screens. Support prototyping and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment. Support procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs. Coordinate, develop, and maintain SLT/BLT testing flows, incorporating takeaways from silicon and correlating them to design for shift-left improvements. Initiate and drive process improvements and preventative actions through root cause analysis and data analytics. Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively. What we need to see: Bachelor’s or Master’s Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience. 3+ years of relevant industry experience in silicon Post-silicon PVT validation and/or high-volume manufacturing testing for complex SoCs, GPUs, CPUs, or similar. Hands-on lab experience with silicon bring-up, lab debug, shmoo analysis, VF characteristics, test content bring-up, and correlation to Si characterization, yield, and coverage optimization. Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, fault analysis, sampling, and computer architecture. Strong data analysis skills, a learning attitude, and prior experience working with large volumes of data. Prior understanding of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production is a plus. Good understanding of firmware/driver structures and their interaction with HW. Problem-solving, debugging, analysis, and logical reasoning skills with

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/silicon-product-engineer-manufacturing-at-nvidia-aa9cb3

Source: https://jobsbylevel.com/jobs/silicon-product-engineer-manufacturing-at-nvidia-aa9cb3

## Cite this page

Level. https://jobsbylevel.com/jobs/silicon-product-engineer-manufacturing-at-nvidia-aa9cb3.

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