# SoC Design Verification Engineer at Intel

Intel is hiring a SoC Design Verification Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/e5741f6f-975d-44fd-9a16-26ef682356f7?utm_medium=ai-agent).

AI Level 1, AI centrality 35 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 35 out of 100)
- Location: US, California, Santa Clara
- Salary: $106k-$149k
- Posted: October 20, 2026
- Apply: https://jobsbylevel.com/go/e5741f6f-975d-44fd-9a16-26ef682356f7?utm_medium=ai-agent

## Description

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel In this role you will be part for the Server SoC Design Validation team, working on next-generation Xeon server product SOCs and IPs. Who You Are: Your responsibilities include but are not limited to: Performs functional logic verification and emulation validation of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products. Behavioral traits that we are looking for: Self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Qualifications: This is an entry-level position and will be compensated accordingly. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Master's degree in electrical or computer science, Engineering or related field. Related coursework/technical experience in/with: 10+ months experience with Silicon Design and/or Validation/Verification. 10+ months experience with x86 Architecture. 10+ months experience with Design and validation experience with global domains (Reset, Clock, Fuse, GPIO, MPP) Preferred Qualifications: Knowledge and Experience with: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Strong debug skills. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. UVM/SV constrained-random coverage-based design verification and Formal Verification methodology. Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Xeon CPU Pre-Silicon, Emulation Validation or Post Silicon Validation. One or more scripting languages to

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-42c680

Source: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-42c680

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