# SoC Design Verification Engineer at Intel

Intel is hiring a SoC Design Verification Engineer. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/37b0c99f-8cf8-4ac8-8a43-a9a958ee7b34?utm_medium=ai-agent).

AI Level 1, AI centrality 29 out of 100. US, Colorado, Fort Collins.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 29 out of 100)
- Location: US, Colorado, Fort Collins
- Salary: $106k-$149k
- Posted: October 22, 2026
- Apply: https://jobsbylevel.com/go/37b0c99f-8cf8-4ac8-8a43-a9a958ee7b34?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=soc-design-verification-engineer-at-intel-a16f2d

## Description

Job Details: Job Description: As a SoC Design Verification Engineer, you will be responsible for ensuring the functionality and reliability of Intel's cutting-edge server SoCs. You will perform functional logic verification and emulation validation to confirm designs meet specifications, uncover potential issues, and implement corrective measures. Through your technical contributions, you will play a vital role in advancing the development of next-generation Xeon server products, driving innovation and excellence in Intel's technology offerings. Business group You will join Intel's Data Center Group (DCG), which is dedicated to delivering leading-edge technologies and solutions for data centers that power the world's digital infrastructure. The team focuses on validating advanced Xeon server SoCs and IPs, providing innovative solutions that enhance performance, scalability, and efficiency. The group's mission aligns with Intel's broader vision of creating world-changing technology that enriches lives globally. Key Responsibilities Perform functional verification and emulation validation of integrated SoCs to ensure designs meet specifications. Develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments. Execute verification plans, analyze system simulation models, and debug power and performance issues. Root-cause failure issues and implement corrective measures in the pre-silicon environment. Collaborate with architects, RTL developers, post-silicon teams, and physical design experts to enhance verification. Document test plans and drive technical reviews with design and architecture teams. Conduct regression and debug tests to integrate security activities and ensure comprehensive coverage. Maintain and improve verification infrastructure and methodology, absorbing learnings from post-silicon validations. Qualifications: This is an entry level position. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications Master's degree in Electrical Engineering, Computer Science or Computer Engineering +6 months of experience in Silicon Design and/or Validation/Verification methodologies and tools. Preferred Qualifications Experience in design verification for complex IPs and SoCs. Knowledge of UVM/SystemVerilog constrained-random coverage-based design verification methodologies. Familiarity with the complete verification lifecycle, including test plan creation, bug debugging, and coverage closure. Skills in developing validation test suites and driving continuous improvement into existing methodologies. Understanding of cache coherency principles in multiprocessor SoCs and layered protocols. Proficiency in scripting languages for automation purposes. Strong debugging skills and ability to independently resolve technical issues. Experience with Xeon CPU pre-silicon, emulation validation, or post-silicon validation. Join us to innovate, learn, and make a meaningful impact in Intel's transformative journey to create world-changing technology. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Colorado, Fort Collins Additional Locations: US, California, Folsom, US, Oregon, Hillsboro Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation,

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-a16f2d

Source: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-a16f2d

## Cite this page

Level. https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-a16f2d.

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